Spectravideo MKI, Сервисное – Техническое руководство

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4.
TIIEORY
OF OPERATION DESCRIPTIOR
SYSTEM
ARCHITECTURE
T he Spe c t rav ideo SVI-3 1 8 / SVI-328 and MarK II home compu t er is a
compu tat ional tool based on a Zi log BOA microcomputer system F igure 4-1.
The Zilog
80A
microproces sor uni t ( �P ) provides cont rol logic , data
manipu lat ion and computat ion capabi lity to the SVI-3 1 8 / SVI-32 8 and Hark II
home compute r . The./-' P uses contents of rea d-only memory ( ROM) to specify
how the computer is to pe r form . An Micro-Sof t Basic compu ter language
in terpre ter is implemented as code store d in the sys tem ROM device s .
Temporary da ta and re s u l t s of comput a t ions can be stored in random-access
memory ( RAM ) . Data in RAM can a l so be�P ins t r uct ions , but is more of ten
Basic language programme instruct ions and computational data .
Bit pa tterns i n ROM specify the type o f activity to be pe rforme d b y the
�P. The se ins truc t ions ( b it pat terns ) cause var ious ope ra t ions to be
pe r forme d .
( 1 ) Read the data at a spec i f ie d addre s s locat ion and place i t in an./' P
reg i s te r .
( 2 ) Write the dat a f rom an�P register t o a speci f ie d addres sab l e
location may be RAM, VDP , PPI or PSG .
( 3 ) Per form compu tat iona l or data compa r i son procedu res on spec i f ied data .
( 4 ) Jump or branch to a loca t ion other than t he next succes s ive memory
locat ion to re trieve the next ins t ruct ion for programme execut ion .
The se jump or branch ope rat ions a re of ten determined by inte rrogat ing
the re su l t or s tatus of an ari thme t i c or log ica l computat ional
operation .
( 5 )
Stop and wai t for inte rrupt .
( 6 ) Branch to and return f rom subrout ines .
(7)
Branch to a vec tore d routine to service inter rupt s and system res tart
operations .
The Zi log
80A
�p
uses a 64K addre ss space . The lower 32K i s dedicated for
ROM dev i ce and per ipheral inter face device s such as PIO and VDP . The upper
32K is dedicated for RAM devices (SOOOH - FFFFH in hexadecimal notation) .
The var ious e lements that share the
64K
address space pos sess unique
a t t ribute s .
CPU ARCBIT!CTUU
A block diagram of the internal arch itecture of the Z-80 CPU i s shown in
Figure 4-2 . The d iagram shows a l l of the major e l ements in the CPU and it
shou ld be re ferred to th roughout the fol lowing descrip t ion .
4.1