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1 6384

1 BIT DYNAMIC MOS RANDOM ACCESS

�!EMORY ( 41 1 6 )

The

4 1 1 6

i s a

1 63 8 4

wor d s b y 1 b i t Dy nam ic MOS

RAM .

I t i s des i gne d f o r memory

ap p l i c a t i on s whe re ve r y l ow co s t and l a rge b i t s t or a g e a re impor t a n t de s i g n
ob j e c t i v e s .

t h e

4 1 1 6

i s f ab r i c a t e d u s i ng a d ou b l e-po l y - l a y e r

N- c hanne l

s i l i c on g a t e p roc e s s

wh i c h

a f f o r ds h i gh s t o r a g e ce l l dens i t y and h igh pe r fo rmance .

The use of

dy na m i c

c i rc u i t r y th rougho u t , inc l u d i ng the s e n s e

amp l i f ie r s ,

a s s u re s m i n i ma l

pow e r d i s s i pa t i on .

Mu l t i p l e x e d add re s s in p u t s p e rm i t the

4 1 1 6

to be packaged i n the s t a nd a r d

1 6

p i n du a l - i n- l i ne package .

The

1 6

p in package p ro v i d e s the h i ghe s t s y s tem b i t

d e n s i t i e s and i s av a i l a b l e i n e i t h e r ce ram i c o r p l a s t i c "

Nonc r i t ic a l c l o c k

t im ing

re q u i remen t s a l l ow u s e o f t he mu l t i p l e x ing t echn i que wh i l e ma i n t a i n ing

h i gh p e r formance .

65536

BIT DYNAMIC MOS

RANDOM

ACCES S MEMORY ( 4864)

The

486 4

ut i l i z e s a t h r e e - po l y N-channe l s i l i c on g a t e p roc e s s wh ich p rov i d e s

h i gh s t o rage c e l l dens i t y , h i gh p e r f o rmance and h i gh re l i ab i l i t y .

The

486 4

us e s a s i ng l e t r ans i s t o r dynam ic s t o ra ge ce l t and a dvan c e d dynam i c

c i rc u i t r y t h roughou t , i nc l u d i ng t he 5 1 2 s en s e amp l i f i e rs , wh i c h a s su r e s t ha t
power d i s s i pa t i o n i s m i n i m i z e d .

Re f re s h cha r a c t e r i s t i c s have be e n cho s e n t o

max i m i z e y i e l d ( low c o s t to us e r ) wh i l e ma i n t a i n ing comp a t ib i l i t y between
Dy nam ic RAM gen e r a t i on s .

The

4 8 64

three-s t a te ou t pu t i s c on t ro l l e d by CAS , ind ep en d e nt of RAS .

A f t e r a

va l i d re a d or r e a d-mo d i f y-w r i t e c yc l e , d a t a i s he l d on the ou t p u t by ho l d i ng
CAS l o w .

The d a t a ou t p i n i s re t u rne d to the h i gh i mpendance s t a t e b y

re t u rn i n g CAS t o a h igh s t at e .

The

4864

h id d e n re f r e s h f e a t u re a l l ows

CAS t o be he l d l ow to ma i n t a i n ou tput d a ta wh i l e RAS is used to e x e c u t e d RAS

on l y re f re sh cyc l e s .

Re f re sh ing i s ac comp l i s he d b y p e r f o rm ing RAS o n l y re f re sh c yc l e s , h id d e n

re f r� sh cyc l e s , or no rma l re a d o r w r i t e c yc l e s on the

1 2 8

a d d re s s comb ina t iuns

of A0

t h rough A 6 du r ing a 2 ms p e r i od .

Mu l t i p l e x e d a dd re s s inpu t s pe rm i t the

4864

t o be packaged i n the s t an d a r d

1 6

p i n dua l - i n- l i ne package .

The 1 6 p in package p ro v i d e s the h i ghe s t s y s t em b i t

d e n s i t i e s a n d i s compa t i b l e w i t h wid e l y ava i l a b l e a u to ma t e d han d l i n g equipmen t .

4 . 46

Содержание MKI

Страница 1: ...SERVICE TECHNICAL MANUAL VOL 1 l SVI318 328 MKI MKII COMPUTER SYSTEM SVI SPECTRAVIDEO ...

Страница 2: ...t ic D iagrams of SVI 801 D isk Control ler Cartridge Schematic D iagrams of SVI 802 Centronics Interface Cartridge and SVI 901 P rinter Schematic D iagrams of SVI 903 Data Cassette and SVI 904 Mono Data Cassette Schematic D iagrams of SVI 603 Game Adaptor Schema tic D iagrams of SVI 8 03 1 6K and SVI 807 64K RAM Cartridge Schematic Diagrams of SVI 805 RS 232 Interface and SVI 701 MODEM Cartridge ...

Страница 3: ...ly pe r iphe ra l s compu ter i nput outpu t device s t e rmina l s p r inte r s e tc ce r t i fied to comply w i th the C l ass B l imits may be at tache d to th is computer Operat i on with non ce rt i f ie d per iphe ra l s is l ik e ly to result in interfe rence to ra dio and TV rece p t i on SVI SPECTRAVIDEO INTERNATIONAL LTD HONG KONG F i r st E d i t i on Second Ed i t ion Th ird Edi t i on...

Страница 4: ... ing input outp ut ope ra t i ons and whe n wa i t i ng to s top a t the end of t he current Micro s oft Bas ic l anguage instruct ion in re sponse to pre s s i ng the s t op key User definab le func t i on keys a l low the ope rator to branch to any of ten spec i f ie d BAS IC programme l ocat ions when press ing one of these keys There are te n keys to spec i fy ten programme loca t i ons Ano th...

Страница 5: ...POWER INDICATOR The power indicator is an LED that monitors the 5V supply When on it indicates the presence of power to the SVI 318 SVI 328 and Mark I I 1 3 ...

Страница 6: ...tic messages and which parts to replace 4 Tables and charts showing plug pin assignments test points and the location of the major components on the controller board 5 Schematices and parts identification information For detailed information on how to repair the disk drives printers or any other peripherals refer to the approperiate service publication To remove the cover refer to Figure 2 1 and u...

Страница 7: ...4 Remove the seven retaining screens 5 Remove the cover 2 2 ...

Страница 8: ...6 Remove the screens on the metal cover 7 Remove the metal cover 2 3 ...

Страница 9: ...To r e assemble u se the above procedures in the rever se order 2 4 ...

Страница 10: ...TROL s igna l norma l ly held HIGH by lK ohm re s i s t or This s igna l wh en pu l le d LOW i e Wh en the adaptor i s i n use d i sab l e s a l l interna l i e SVI 3 18 SVI 328 and Mark II I 0 addre s s decod ing and inv er ses A1 5 Indicates to Z80A CPU tha t the addre s se d memory or I O dev ices a re not ready for da ta trans fer Whe n th i s s igna l i s pu l l ed LOW the CPU beg ins a RESET...

Страница 11: ...ica tes when the a ddress b us is ho lding a va lid memory a dd ress Buf fere d INPUT OUTPUT REQUEST s igna l This s ignal indicates the lower 8 b its of the address b us are holding a val id I 0 device address an d is at high s ta te i e inact ive during the INTERRUPT cycle Buffere d READ signa l Th is s ignal in dic a te s tha t the Z80A CPU is wan t ing to read data f rom memory or an I 0 devic...

Страница 12: ...the memory 32K Addr OOOOH 7FFFH and disables the BASH ROH on board through the ROMDIS signal Buffered MEMORY BANK CONTROL signal Pulling this signal LOW enables the bank 22 por tion of the memory 32K Addr 8000H FFFFH and disables the usser RAH on board through the RAMDIS signal Buffered MEMORY BANK CONTROL signal Pulling this signal LOW enables the bank 21 portion of the memory 32K Addr OOOOH 7FFF...

Страница 13: ...I S ti I Oa SUPER lXf olt NOf A fMITAl CASI SVI J18MK1i COMPUTE 0 THE SVI 318MKII SYSTEM PERIPHERAL MAP StNGLI SLOT llC PANOIIII SVI eG Z I r I i WIIII SU Y SVt l01 OUIC SHOT I JOYSTICK S 11 101 I LljiJJ QUtCKSH T Ill 1t UI KI OT II JOl STICI SYI 102 GIRAPMIC TAIUT IVI IOI 0 I N ...

Страница 14: ... l g 5 0 ii S GUSLOT n 1 1 5 h t IX ANOIO IVI OOZ I i I 9 g 8 5 l h N 1 i v Dl MONITOIII SV HOMITY CCI DATA CASSlnl SYI IOt VI 328MKH CO PUT R P OWU SU _Y SVI 201 QUICK SHOT I JO iiTICI SYI IOI Ql tCI 5HOT II JOYSTICK 5VI 10 II GAAI HtC fAII lT SY1 101 ...

Страница 15: ... 90 MODEM ITELEPHONEI SINCLE UNIT ADAPTER 18 602 IUPAHOUt COVER MODEM CARTRIDCE 318 701 BOCOI UMN MATRIX PRINTER 318 901 PRINTER CARTRIDCE 16K RAM CARTRIDCE 318 803 2K RAM CARTRIDCE 18 804 MOTHERBO rO UPANOlR 5l8601 IWtT M 7 UPA NSION 101 1 sv FlOPPY DISK DRIVE 318 901 CENTRONIC INTERFACE 316 602 OTHERS 5 C FLOPPY DISK DRIVE 318 902 DISK DRIVE CARTRIDCE 18 801 N M N ...

Страница 16: ...PUTER TESTING RESULT If the printer falls to print t he me s sage it indicates that errors may occur in any one of the fo llowings i CPU ii OUTPUT BUFFERS i li USER RAM 2 If no errors occur in the test ing of the USER RAM the message USER RAM OK is printed However if an error does occur the message USER RAM ERROR is printed and the following information will be given ADDRESS XXXX DATA WRITE YY DAT...

Страница 17: ...d otherw i se CAS SETTE L INE ERROR message is printed to indica te CA SSETTE LINE is not func t i oning proper ly The re are our ways to te st CASSETTE LINE the procedures are as fol low s a input CASW O low output CASR l hi gh if not ERROR TEST 1 CASW CASR message is printed input ME O low ou tput R E l high if no t ERROR TEST 1 ME RE message is printe d b input CASW O low output CASR l high if ...

Страница 18: ...RROR OUTPUT 7 I NPUT O 8 ERROR OUTPUT 8 INPUT 4 9 ERROR OUTPUT 9 INPUT 5 10 ERROR OUTPUT 1 0 INPUT 7 All ou tput O low input 1 h igh A KEYBOARD LINE TEST ING COMPLETED me s sage is p r inted at the end when erro rs occur only 9 JOYST ICK te s ting JOYST ICK 1 GREEN CUR SOR JOYST ICK 2 RED CURSOR l erro r in 7 8 and 9 check PSG and PP I 10 In CP M 2 22 ve rsion sy stem d i sk enclo sed memtst com m...

Страница 19: ... an 809 exe rc i s er with a spe c i a l c ab l e s e t Th is exerc i se PCB c an b e used in a s t and a l one mode bu i l t i n to a t e s t s t a t i on or used in a te s t er for f i e ld service T he exerc i s er enab l e s t he user to per form all a d j u s tment s and checks requ i re d on t h e SA2 00 d r i ve I t ha s no i n t ell igent d a t a hand l i ng capabi l i t ie s b u t can wr ...

Страница 20: ...access head to adjacent track in same d i rec tion previous ly moved then re turn to des ired track c Repeat step a d If data is no t recove red er ror is not recoverable Wri te Error If an error occurs during a wri te operat ion i t w i l l be detected on the nex t revo luti on b y doing a read opera t ion commonly ca l led a write check To correct the er ror another w ri te and check operation m...

Страница 21: ...riage binds c To recover from a seek erro r reca l ibrate to track 00 and perform another seek to the origina l track Another a lternative is to perform a read I D to determine on which track the head is located and compensate accordingly 3 6 ...

Страница 22: ...ing t he p rogramme is runni ng and make sure the p rog ramme w l l no t be in terrup t e d or termina ted by the s hock in the te st 4 P re s s STOP ob serve that p rogramme is temporary s topped by th is Pre ss STOP aga in and no te that t he prograinme w i l l cont inue 5 Pre s s CRTL STOP the p rogramme should te rminated by th is command and t he OK p rompt reappe a r 6 Pre s s F4 L ist t h e...

Страница 23: ...RPH RIGH GRPH and then simu l taneou s ly press severa l keys to check the graph ic symbo ls are d i s p layed 1 6 Turn the power off Diagno s t ic Test 1 Connect the su per expander SVI 601 to the computer 2 Insert t he pr inter in ter face SVI 802 cartr idge in any one of the s lots ex cept slot 6 3 Connect the pr inter SVI 901 to the printer inter face through a flat cable 4 Insert the Tes ter ...

Страница 24: ...comput e r off Ca s s e t te Int er fa ce Te st 1 Co nnect the data ca sset te SVI 903 to the comput e r through the cas s e t t e int er face s ocke t at t he back 2 Tu rn on the power 3 Type SOUND ON and p re s s ENTER 4 Ins e r t a Co l our P a t t e rn t ape into the c a s s e t te 5 Type CLOAD and pre ss ENTER 6 P r e s s PLAY button on the casse t t e 7 The p rogramme in the tape i s being l...

Страница 25: ...be l is te d f rom t he p r inte r 1 9 Turn off the powe r D isk Bas ic Tes t 1 Insert the d i sk control ler ca r t r i dge SVI 801 to the slot SK6 in the super expande r 2 Connec t 2 disk drive SVI 902 to the d i sk cont ro l l e r through the f la t cab les 3 Inse r t the BASIC d i s k to the disk d rive A 4 Tu rn t he disk l ock t o ve r t i ca l pos i t i on and turn on the power in compute r...

Страница 26: ...programme 1 6 Type and pre s s ENTER to cl ear the memory 1 7 Type KILL l CI R and pre ss ENTER to erase the f i le CIR wait unt i l t he computer p r i nt OK 18 Type FILES and pre s s ENTER ob se rve tha t the f i l e CI Ru shoul d di sappe a r 1 9 Turn o f f the power CP M D isk Tes t 1 Insert the 64K RAM ca rtr idge into any s l o t s of SVI 601 super expander except SK6 Set the swi tch BK2i an...

Страница 27: ...t e in drive B and p re s s ENTER 1 3 Wa i t unt i l verifying t rack 39 i s shown on the screen 1 4 Type i an d pre ss ENTER wai t un t i l command A reappear on the scre en 15 Type DIR B and p re s s ENTER to l i s t the directory in the copy d iske t te in d r i ve B to con f irm that the copy ing is comp l e te d 16 Type ERASE B and pre s s ENTER to erase the f i l e s in the d iske t te in d ...

Страница 28: ...ch i s on right hand s i d e of the mach ine Be sure the power cab l e i s connec t e d to the compu ter and rep l ace the brown fuse Se l ect correc t TV channe l Be sure a l l video cab l e s are secu re ly fas t e ne d Ad j us t TV the vo lumn control and co lour l e ve l of your TV Use osc i l los cope to check IC23 pin 4 and IC36 P in 39 C8 and 7805C pin 2 C 1 1 4 and 7 8 1 2 C pin 3 7 9 1 2C...

Страница 29: ...n l c a c 7 4 I L 7 C 73 C7S ICU Q CJ 711 1 2 I O C81 fJ 82 c s J C6 02 OGE O CBJ I I I m eP oo 0 I I 1 00 0 0 C7 cx JO r COO oi c IDl l U r v t 51 4 g R33 r OWER SOCKET POWER SWITCH JOY STICK JOY o tJU o o o o SK3 I STIC K Qoe g _ __ __ _ R320 _ _ o o o o go gn n og J O LL n R30 ...

Страница 30: ...D es O C 82 c s C71 D e I C 4 r j C 74 IC45 1 1c r gf ckLJ CJ 7612 Kl IC44 u n 8 c 87 0 3 RIDCE 0 2 ocm o CBJ B o oo n I III U I 0 D C 7 Oc O l l 6 1 r J SX ti l l I 0 R3J POWER SOCKET POW ER SWIT CH JO Y STICK JOY u B I B J r o u L_j LJ S Sl 3 I STICK 0 ct s c o 1c41 0 1 0 SIO RJO ...

Страница 31: ... WRITE 260 DATA BE REM I CP HL 270 DATA 2 F REM I CPL 2 80 DATA 77 REM LD HL A SAVE BACK 290 DATA CO REM RET NZ 300 DATA 23 REM 1 INC HL 3 1 0 DATA 7C REM 1 LD A H EXIT FOR HL 8000 3 20 DATA FE 80 REM I CP 80H 330 DATA 20 F3 REM JR NZ CHKSZ1 3 40 DATA C9 REM I RET HL SIZE 3 50 I 360 I PSG PORTB ROHENl ROMENO CAP BK32 BKJl BK22 BK2 1 CART 370 I D7 D6 05 D4 D3 D2 D l DO 380 I IN PSG DATA 90H 390 I O...

Страница 32: ... 6 1 0 DATA 47 REM I LD B A 6 20 DATA E6 F7 REM I AND 1 1 1 1 0 1 1 1B BANK 3 1 ON 630 DATA D3 8C REM I OUT 8CH A 640 DATA CD OO DO REM I CALL CHKSIZ RESULT IN HL 650 DATA 22 44 DO REM I LD BK3 1 HL DATA SAVE 660 DATA 7 8 REM I LD A B ORG BANK COND 670 DATA D3 8C REM I OUT 8CH A 680 DATA FB REM I EI 690 DATA C9 REM I RET 700 DATA 00 00 REM I BK2 1 DS 2 MEMORY SIZE OF BANK 2 1 7 1 0 DATA 00 00 REM ...

Страница 33: ...5 1 91 LINE 2 5 5 0 0 1 9 1 70 80 90 check p l ot 1 00 FOR Y O TO 1 92 STEP 7 110 LPRINT CHR 8 1 20 FOR X O TO 255 1 30 A H80 140 1 50 1 60 1 70 1 90 2 1 0 220 230 FOR B O TO 6 PLOT 7 DOTS A A ABS POINT X Y B 1 5 2 B NEXT B LPRINT CHR A PRINT 1 BYTE BIT PATTERN NEXT X LPRINT CHR HA NEXT LINE NEXT Y 3 18 ...

Страница 34: ...it in an P register 2 Write the data from an P register to a specifie d addressable location may be RAM VDP PPI or PSG 3 Per form computat ional or data comparison procedures on speci f ied data 4 Jump or branch to a location other than the next successive memory location to retrieve the next instruct ion for programme execut ion These jump or branch operations are of ten determined by interrogati...

Страница 35: ...328 SV GND C1 0CK I SYSTEM AND CPU CONTROL OUTPUTS FIG 4 2 I CPU CONTROL INPUTS E G _ Cl tU TIMING X 2 JmsriCK MEI fJFCi BANK FIRE l3I 1I ltN 1 c NI roL DATA BUS INTERFACE REGISTER ARRAY ADDRESS LOGIC AND BUFFERS ALU IT ADDRRUBUS Z80CPU Block Diagram 4 2 ...

Страница 36: ... have been trans f e rred to the addres s l ines When a programme j ump occu rs t he new va l ue i s automat ica l ly place d in the PC overriding the incrementer 2 S t ack Point e r SP The s t ack po inter ho lds the 1 6 b i t add re s s of the current top o f a s t ack loca ted anywhe re in ex t e rnal sy s t em RAM memory The ex ternal stack memory is or igan i zed as a la s t in first ou t LI ...

Страница 37: ...fy a d i sp l acement is spec i f i e d as a two s comp le me nt sig ne d in tege r Th i s mode of a dd re s s ing grea t ly s imp l i f ies many t ypes of programme s e spec i a l ly whe re tab les of data are use d 4 Inte rrupt Page Address Reg i ster I The Z 80 CPU can be ope rated in a mode where an ind i rect ca l l to any memory l ocat ion c an be ach ieve d in response to an i n terrupt The...

Страница 38: ...ons such as indicat ing whe ther or not the result of an operat ion is e qual to zero The p rogramme r se lects the accumu lator and flag pa i r that he w i sh e s to work wi th a s ing le exchange instruc t i on so that he may eas i ly work with e i ther pai r GENERAL PURPOSE REGISTERS The re are two ma tche d s e t s of general purpose registers each se t containing s ix 8 b i t reg i sters that...

Страница 39: ... OR Compa re Le f t or right sh i f ts or rot ates a r i thme t ic and log i ca l Increment Decrement Set b i t Reset bit Te st bit INSTRUCTION REGISTERS AN D CPU CONTROL As each instruc t ion is f etche d from memory it is placed in the ins truc t ion reg i s ter and decoded The c ontrol sect ions performs this func t ion and then gene rat es and supp l ie s a l l o f the cont rol si gna l s nece...

Страница 40: ...nges b lock transfers and searche s 8 b it a r i t hme t ic and logic ope rat ions Gene ra l pu rpose arithmet ic and CPU contro l 1 6 b i t a r i t hme t i c operat i ons J Rot ates and sh i f ts c Bit se t re set and test operat ions C Jumps J Ca l l s re t u rns and re starts Input and output operat ions A va r i e t y of a ddress ing modes are implemented to pe rm i t e f f i c ient and fast d...

Страница 41: ...r IX d X X 1 1 0 1 1 1 0 1 DD 3 5 1 9 0 1 1 E 0 1 r 1 0 1 1 00 H d 1 0 1 L LD r IY d r IY d X X 0 1 1 1 1 1 1 0 1 FD 3 5 1 9 1 1 1 A 0 1 r 1 1 0 d LD HL r HL r X X 0 1 1 1 0 r 1 2 7 LD IX d r IX d r X X 1 1 0 1 1 1 0 1 DD 3 5 1 9 I co 0 1 1 10 r d LD IY d r IY d r X X 0 1 1 1 1 1 1 0 1 FD 3 5 1 9 0 1 1 1 0 r d LD HL n HL n X X 00 1 1 0 1 1 0 3 6 2 3 1 0 n LD I X d n I X d n X X 1 1 0 1 1 101 DD 4 ...

Страница 42: ... 0 n n 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 000 1 0 1 001 I FF the c o n t e n t o f the i n t e r rupt enab l e f l i p f l o p I FF i s cop i e d i n t o the P V f l a g For a n e xp l an a t i o n o f f l a g no t a t i on and symb o l s for mnemo n i c t ab l e s see Symbo l ic N o t a t i on s e c t ion fo l l ow ing ta b l e s 0 1 0 OA 1 2 7 01 0 1A 1 2 7 0 1 0 3A 3 4 1 3 t 0 1 0 0 2 1 2 7 0 1 0 1 ...

Страница 43: ... 0 1 DD 4 4 1 4 1 0 HL 00 1 00 00 1 2 1 1 1 SP f n n LD IY nn I Y nn X X 1 1 1 1 1 1 0 1 FD 4 4 1 4 00 1 00 001 2 1 f n n I 0 LD HL nn H nn l X X 00 1 0 1 0 10 2A 3 5 1 6 l i L nn 1 n n 7 LD d d nn ddH nn 1 X X 1 1 1 0 1 1 0 1 E D 4 6 20 ddL nn 0 1 d d l 0 1 1 n 7 n LD I X nn I X H nn l X X 1 1 0 1 1 1 0 1 DD 4 6 2 0 I X L t nn 00 1 0 1 0 1 0 2 A n n LD nn HL nn l H X X 00 1 00 0 1 0 2 2 3 5 1 6 n...

Страница 44: ... 1 AF I rot SP 1 IX 1 1 1 00 1 0 1 E 5 rot SP SP 2 PUSH IY SP 2 IYL X X 1 1 1 1 1 101 FD 2 4 1 5 SP 1 IY H 11 100 101 E 5 POP qq qqH SP l X X 1 1 qqO 00 1 1 3 10 qqL SP SP SP 2 POP IX IXH SP l X X 1 1 0 1 1 1 0 1 DD 2 4 1 4 IXL SP 1 1 1 00 001 El SP _ SP 2 POP lY IY H SP l X X 1 1 1 1 1 1 0 1 FD 2 4 1 4 IYL SP 1 1 1 00 001 E1 SP SP 2 NOTES dd i s any of the reg i s t e r pa i rs BC DE HL SP qq i s...

Страница 45: ... ry HL I 1 HL reg i s t e r bank exchange EX SP HL H t SP 1 X X 1 1 1 00 01 1 E3 1 5 1 9 L SP E X SP IX IXH SP 1 X X 1 1 01 1 1 0 1 DD 2 6 2 3 I X L SP 1 1 1 00 0 1 1 E3 EX SP IY IY H tt SP X X 1 1 1 1 1 101 FD 2 6 2 3 I N IY L e SP 1 1 1 00 0 1 1 E3 1 i LDI DE f HL X X t 0 1 1 101 1 0 1 ED 2 4 1 6 Load ltL DE DE 1 1 0 1 00 000 AO into DE HL HL 1 increme n t the BC BC 1 pointers and decreme n t th...

Страница 46: ...0 HL t HL 1 BC BC 1 R e p e a t unt i 1 B C 0 2 j CPI A OIL t t X t X t 1 1 1 1 0 1 1 0 1 ED 2 4 1 6 HL t HL 1 1 0 1 00 00 1 A1 I BC t BC 1 V CD CPI R A HL t t X t X t 1 1 1 1 0 1 1 0 1 ED 2 5 2 1 I f BC 0 and A HL HL t HL 1 10 1 1 0 001 B 1 2 4 1 6 I f B C 0 o r BC t BC 1 A HL Repe at unt i l A HL or BC 0 CPD A HL t t X t X 1 1 1 1 0 1 101 ED 2 4 1 6 H L HL 1 10 1 0 1 00 1 A9 BC t BC 1 ...

Страница 47: ... 1 HL HL 1 1 0 1 1 1 001 BC BC 1 Repe a t un t i l A HL or BC 0 NOTES QD P V f lag is 0 i f t he r e su l t of BC 1 0 o t he rw i se P V 1 GD Z f lag is 1 i f A HL o therw i se Z 0 ED 2 5 2 1 B9 2 4 1 6 I f BC 0 and A HL I f B C 0 o r A HL qo ...

Страница 48: ...e s Conunent s ADD A r A f A r 1 t X t X v 0 t 10 oool r 1 1 4 r Reg j ADD A n A t A n l r X l X v o t 1 1 1 1 0 2 2 7 000 B n 00 c 0 1 0 D ADD A HL A f A HL J X t X v 0 t 1 0 1 1 0 1 2 7 0 1 1 E ADD A l I X d A A O X d t t X X v 0 t 1 1 0 1 1 1 0 1 D D 3 5 1 9 1 00 H Ltl 1 0 pool 1 1 0 1 0 1 L r 1 d ADD A IY d A t A IY d t l X t X v 0 1 1 1 1 1 1 1 0 1 F D 3 5 1 9 1 0 1 1 0 d ...

Страница 49: ... I b i t s rep lace the in OR s A A v s l l X 0 X p 0 0 ITg ADD se t above XOR s A A s t t X 0 X p 0 0 loti CP s A s 1 t X X X v 1 t l l l l l I 0 f INC r f r l t s X X X v 0 00 1 1 4 r r o r INC HL HL HL l t t X t X v 0 00 1 1 0 29 1 3 1 1 INC IX d IX d t t X t X v 0 1 1 0 1 1 1 0 1 DD 3 6 2 3 OX d 1 00 1 1 0 29 d INC IY d IY d t X X t X v 0 1 1 1 1 1 1 0 1 FD 3 6 2 3 IY d l 00 1 1 0 2g d ...

Страница 50: ...DEC m m m 1 t X t X v 1 1 101 1 m i s any o f r HL IX d I Y d as shown for INC DEC s ame f o rma t and s t a t e s a s INC Rep l ace l l ool w i th lloll in opcode r 1 ...

Страница 51: ... l c on t e nt i n to a d j u s t pa cke d BCD accumu l a t o r f o l low ing a dd o r subt r a c t w i th pack e d BCD op e ra nd s CPL A A 0 X t X 1 00 1 0 1 1 1 1 2F 1 1 4 Comp lement accumu l a t o r one s I co I c omp l eme n t NEG A t 0 A l r X X X v 1 t 1 1 1 0 1 1 0 1 ED 2 2 8 Nega t e a c e 0 1 000 1 00 44 tl 10 s c om p l eme n t CCF CY t CY 0 X X X 0 00 1 1 1 1 1 1 3 F 1 1 4 Comp l emen...

Страница 52: ...1 1 0 1 1 0 1 E D 2 2 8 mode 0 0 1 000 1 1 0 46 IM1 S e t i n t e rrupt X X 1 1 1 0 1 1 0 1 E D 2 2 8 mode 1 1M2 S e t i n t e r r up t X X 1 1 1 0 1 1 0 1 ED 2 2 8 mode 2 0 1 0 1 1 1 1 0 5 E NOTES I FF i n d i c a t e s the i n t e rr u p t enab l e f l ip f l op 0 1 r 1 CY i n d i ca t e s the ca r r y f l i p f l op oqt i n d i c a t e s i n t e rrup t s a re n ot s am p l e d at t he end of EI...

Страница 53: ... 0 1 DE 0 1 s s 1 0 1 0 1 0 HL 1 1 SP SBC HL s s H L HL s s CY t T X X X v 1 t 1 1 1 0 1 1 0 1 E D 2 4 1 5 0 1 s sO 0 1 0 ADD I X pp IX l X pp v X X 0 r 1 1 0 1 1 1 0 1 2 4 1 5 E2 Reg J 0 1 pp 1 001 00 BC 0 1 DE 1 0 I X 0 1 1 SP N ADD IY rr I Y IY rr X X X 0 t 1 1 1 1 1 1 0 1 FE 2 4 1 5 r r Reg 00 r r 1 001 00 BC 0 1 DE 1 0 I Y 1 1 SP INC s s s s 5 5 1 X X 00 s sO 0 1 1 1 1 6 INC I X I X IX 1 X X ...

Страница 54: ...0 1 DD 2 2 1 0 00 1 0 1 0 1 1 2 B DEC IY I Y IY 1 X X 1 1 1 1 1 1 0 1 FD 2 2 1 0 00 1 0 1 0 1 1 2 B NOTES ss i s any of t h e reg i s t e r pa i rs BC DE HL S P pp i s any of the r eg i s t e r p a i r s BC DE I X S P r r i s any o f t h e reg i s t e r pa i rs BC DE I Y SP rl N ...

Страница 55: ... RLCA I 7 o I X 0 X 0 t 00 000 1 1 1 07 1 1 4 R o t a t e l e f t A c i rc u l a r accumu l a t o r RLA L X 0 X 0 00 0 1 0 1 1 1 1 7 1 1 4 Ro t a t e l e f t A accumu l a t o r l 1 Ro t a te r i ght I N RRCA 7 0 X 0 X 0 X 00 00 1 1 1 1 OF 1 1 4 N A c i rc u l a r r accumul a t o r RRA L l 7 0 I J X 0 X 0 t 00 0 1 1 1 1 1 I F 1 1 4 Ro t a t e r i ght A ac cumu l a t o r ...

Страница 56: ...0 1 1 CB 2 2 8 R o t a t e l e f t 00 000 r c i rcu l a r reg i s t e r r 1 1 00 1 0 1 1 CB 2 4 1 5 r Reg 000 B 00 000 1 1 0 00 1 c 0 1 0 D 1 1 0 1 1 1 0 1 DO 4 6 2 3 0 1 1 E 1 1 00 1 0 1 1 CB 1 00 H d 4 1 0 1 L 00 000 1 1 0 1 1 1 A I 1 1 1 1 1 1 0 1 FD 4 6 2 3 N 1 1 00 1 0 1 1 CB d I n s t r uc t i on 00 000 1 1 0 f o rmat and s t a t e s a re 0 1 0 a s shown f o r RLC s To f o rm new ope ode 00 ...

Страница 57: ...1 3 0 t X t A HL 7 4 1 3 o 7 4 1 3 o 1 t t X I A HL 0 0 0 0 0 0 X p 0 ru X p 0 X p 0 t t o t j u t X p 0 t I N X p 0 1 1 101 1 0t ED 2 5 t8 Rot a t e d i g i t Ot t01 l l t 6 F l e f t and r ight be twee n t h e accumu l a t o r and loca t ion HL X p 0 1 1 t o t lOt E D 2 5 1 8 The content 01 t OO t l l 6 7 o f the uppe r ha l f o f the accumu l a t o r i s una f f ec t e d ...

Страница 58: ... z f HL b X 1 X r X X 0 1 1 00 1 0 1 1 CB 2 3 1 2 00 1 c 0 1 b 1 1 0 0 1 0 D B I T b I X d z IY d b X T X r X X 0 1 1 0 1 1 1 0 1 D D 4 5 2 0 0 1 1 E 1 1 00 1 0 1 1 CB 1 00 H d 1 0 1 L 0 1 b 1 10 1 1 1 A I b B i t Te s t e d N BIT b IY d IY d b t t z X X X X 0 1 1 1 1 1 1 0 1 FD 4 5 2 0 000 0 1 1 00 1 0 1 1 CB 001 1 f d 0 1 0 2 0 1 b 1 1 0 0 1 1 3 1 00 4 1 0 1 5 1 1 0 6 1 1 1 7 SET b r r b 1 X X 1...

Страница 59: ...X d IY d X X X X 1 1 0 1 1 1 1 00 1 d b j g NOTES The no t at ion m b ind icates b i t b 0 to 7 or locat ion m 1 0 1 DD 4 0 1 1 CB 1 1 0 6 2 3 To form new opcode rep l ace of SET b s w i th g F lags and t ime s t a t e s f o r SET instruct ion 0 N q ...

Страница 60: ...i t i on X X 1 1 cc 0 1 0 3 3 1 0 000 NZ non cc i s t r u e n zero PC nn n 001 Z zero o th e rw i se 0 1 0 NC non co n t i nu e carry 0 1 1 C carry 1 00 PO p a r i t y I I odd N 101 PE par i t y qo even 1 1 0 P s ign p o s i t i v e JR e PC f PC e X X 00 0 1 1 000 1 8 2 3 1 2 1 1 1 M s ign negat ive of e 2 JR C e I f C 0 X X 00 1 1 1 000 38 2 2 7 I f cond it ion co n t i nue e 2 not me t I f c 1 2...

Страница 61: ... i PC PC e is me t JP HL P C E H L X X 1 1 101 001 E9 1 1 4 JP IX P C t I X 0 X X 1 1 0 1 1 1 0 1 DD 2 2 8 1 1 1 0 1 00 1 E9 I co JP IY PC IY X X 1 1 1 1 1 1 0 1 FD 2 2 8 N 1 1 1 0 1 00 1 E9 DINZ e B 4 B 1 X X 00 010 000 1 0 2 2 8 I f B 0 I f B 0 e 2 c o n t i n u e I f b r o 2 3 1 3 I f B 0 PC PC e NOTES e r e p r e s e n t s t he e x t e n s i on in t he re l a t i ve a dd r e s s ing mode e i s...

Страница 62: ...0 1 CD 3 5 1 7 S P 2 P C L n P C n n n CALL cc nn I f c o n d i t i on X X 1 1 cc 1 00 3 3 1 0 I f c c i s c c i s f a l s e n fa l s e co n t i n u e o t h e rw i s e same n 3 5 1 7 I f cc i s a C A L L nn t r ue RET P C S P X X 1 1 00 1 00 1 C9 1 3 1 0 P C SP 1 RET cc I f cond i t i on X X 1 1 cc 000 1 1 5 I f cc i s c c i s f a l se f a l se I 0 N cont inue 1 3 1 1 I f c c i s o t h e rw i se t...

Страница 63: ...y odd RETN 1 R e t u r n f co P X X 1 1 1 0 1 1 0 1 ED 2 4 1 4 1 0 1 PE p a r i t y n o n m a s k a J l e ven i n t e r r up t 0 1 000 1 0 1 45 1 1 0 P s ign p o s i t i ve 1 1 1 M s i gn I 0 nega t i ve r RST p S P 1 PC H X X 1 1 t 1 1 1 1 3 1 1 _ __ _ S P 2 PC L 000 OOH PC H 0 00 1 OBH PC L p 0 1 0 l OH 0 1 1 l BH 1 00 20H 1 0 1 2 8 H 1 1 0 3 0 H 1 1 1 38H NOTE RETN l o a d s I FF 2 I F F 1 ...

Страница 64: ...i 1 B 0 Opcode c 7 6 5 43 2 1 0 He x 1 1 0 1 1 0 1 1 D B n 1 1 1 0 1 1 0 1 ED 0 1 r 000 1 1 1 0 1 1 0 1 ED 1 0 1 00 0 1 0 A2 1 1 1 0 1 1 0 1 E D 1 0 1 0 1 0 1 0 B 2 1 1 1 0 1 1 0 1 ED 1 0 1 0 1 0 1 0 AA 1 1 1 0 1 1 0 1 ED 1 0 1 1 1 0 1 0 BA No o f N o o f M B z t e s Cyc l e s 2 3 2 3 2 4 2 s I f B O 2 4 I f B 0 2 4 2 5 I f B 0 2 4 I f B O N o o f T S t a t e s 1 1 1 2 1 6 2 1 1 6 1 6 2 1 1 6 Comm...

Страница 65: ... A7 B B 1 1 0 1 1 0 0 1 1 B3 I f B f 0 B to A8 A 1 5 HL HL 1 2 4 1 6 Repe at unt i l I f B 0 B 0 1 OUTD C H L X t X X X X t 1 1 1 0 1 1 0 1 ED 2 4 1 6 C t o A 0 A7 B _ B 1 1 0 1 0 1 0 1 1 AB B to As A15 HL HL 1 I N M 0 OTDR C HL X t X X X X t 1 1 1 0 1 1 0 1 ED 2 5 2 1 C to A0 A 7 I B B 1 1 0 1 1 1 0 1 1 I f B O B to A8 A 15 H L HL 1 2 4 16 Repeat unt i l B 0 I f B 0 NOTE m I f the re su l t of B ...

Страница 66: ... 8 b i t s u b t r ac t subtract w i th c a r ry comp a r e and neg a t e a ccumu l a t o r Log ica l ope ra t i on s 8 b i t inc r ement 8 b i t decrement 1 6 b i t a d d 1 6 b i t add w i th carry 1 6 b i t subt ract w i th c a rry Rot a t e acc umu l a to r R o t a te and s h i f t l o c a t i ons Rot a t e d ig i t l e f t and r i ght D e c i ma l a d j us t accumu l a t o r Comp l emen t accu...

Страница 67: ...of the a ccumu l a tor Add Subtract f l a g N 1 i f the pre vious ope rat ion was a sub t ract H and N f lags are used in con j unc t i on w i th the dec ima l adjust ins truc t i on DAA to p rope r ly correct the re sult into packed BCD forma t fo l lowing a dd i t ion or subtract ion us ing ope rands w i th packed BCD format Carry L ink f l ag C 1 i f the ope rat ion produced a carry from t he M...

Страница 68: ... b i t loca t ion for a l l the addre s s ing modes a l lowed for that ins truct i on Any one o f the two index reg is ters IX o r IY Ref re sh counte r 8 bit va l ue in range 0 25 5 1 6 b i t va lue in range 0 65 53 5 4 35 ...

Страница 69: ... I ON REGISTER LINE CONTROL REG ISTER MODEM CONTROL REGISTER LINE STATUS REG ISTER FD 1 793 STATUS REGISTER FD 1 7 93 COMMAND REG I STER FD 1 793 TRACK REGISTER FD 1 7 93 SECTOR REG ISTER FD 1 793 DATA REGISTER READ INTRQ AND DRQ 0 P P INS DISK SELECT REGISTER BI T 0 0 TO SELECT DISK 1 BIT 1 0 TO SELECT DISK 2 DEN SITY SELECT REG ISTER BIT 0 0 FOR DOUBLE DEN BIT 0 1 FOR SINGLE DEN ADDRES S REGISTE...

Страница 70: ...an p revent the CPU f rom prope r ly re fre s h ing dynam ic RAMs Da ta Bus input ou tpu t ac t ive H i gh 3 state D D 7 cons t itute an 8 b it b id i re c t iona l data bus use d for data exchanges w i th memory and I O Halt S t a te output act i ve Low HALT ind icates that the CPU has executed a Ha l t instruct ion and is awa i t ing e ithe r a non maskab l e or a maskab l e i n t e rrupt w i th...

Страница 71: ...Reset input active Low RESET initial izes the CPU as fo l lows that The gate It reset s the interrupt enab le fl ip f lop clears the PC and Registers I and R and sets the interrupt status to Mode 0 During re set time the address and data bus go to a high impendance state and al l control output signa l s go to the inactive state Note that RESET must be act ive for a minimum of three ful l clock cy...

Страница 72: ...y on a spec i f ic p lane to show through a l l p l anes in f r ont of that p l ane mus t be t r ansparent at tha t p o i n t The f i r s t 32 p lane s Figure 4 5 each may con t a in a s ing l e spr i te Spr i te a re pat te rn ob jects whose po s i t i ons on the sc reen are de f i ne d by hor i zont a l and ve r t i c a l coo r d i na t e s in VRAM The a r e a s of the Spr i te P l anes out s id...

Страница 73: ...e Pa t t e rn plane The VDP ha s fou r vided co lour display modes that appea r on the Pa t t e rn P lane Gr aph i cs I mode Graph i c s I I mode Text mod e and Mu l t ico lou r mode Graph ics I and Graph ics I I modes cause the Pa t te rn P lane to be broken up into g roups o f 8 x 8 pixe l s ca l led pat te rn pos i t i ons S i nce the fu l l i mage i s 256 x 1 92 p i xe l s there are 32 x 34 pa...

Страница 74: ...i gh and low order VRfu add re s s and ou t p u t data by t e s ADO i s the mo s t s i g n i f icant b it and i s used only for da ta and no t fo r add res s i ng VRAM row a dd re s s st robe VRAN co lumn add re s s st robe VRAM wri t e s t robe 1 0 7 MHz crys t a l inputs VDP out put c l ock XTAL 24 Typ ica l ly not used RESET Th i s p in is a t r i l e ve l input p in When it is be l ow 0 8 vo l...

Страница 75: ...s a r y h o r i z o n t a l and ve r t i c a l s y nchro n i z a t i on s s igna l s as we l l a s lum inance a n d c hr o m i n a nc e in f o rma t i on In mon i t o r app l ic a t i o n s t he re q u i reme n t s o f t h e mon i tor s h o u l d be s t ud ie d t o de t e rm in e i f the VDP can be c onnec t e d d i re c t ly t o i t In some c a s e i t may be ne c e s s a r y to p rov i d e a s i...

Страница 76: ... ieve d by a spec ia l l eve l di s t i nc t i on ma de by the R Y and B Y VDP outpu t s When e x t e rnal v ideo is e n t e re d the se two ou tputs g o t o the e quiva l ent o f the s ync pe rce ntage l eve l of the b lack wh i t e swing in the luminance ou tput i e the co l our d i f f e rence outputs a re norma l ly sw ing ing between the luminance b lacm wh ite vo ltage l eve l s and it is on...

Страница 77: ...EXTE RNAL VIDEO INPUT BACKDROP CSOL I O COLOR I PATTERNS L O 1 ICHARACTE R O R I ENTEOJ I I I I I I SPRITES OBJECT O R I ENTE O J VDP DISPIAY PIANES F I G 4 4 VDP DISPIAY PLANES F I G 4 5 4 44 E XTERNAI VIDEO SACXOROP l t ANE ...

Страница 78: ...b l ock o f RAM s RMl w r i t e f rom the R W 0 and MPX s i gna l When low the RAM s wi l l acce p t data f rom t he bus t he RM1 s a re r ea d ing the bus R W 0 is h i gh read When h i gh the RAM s w i l l output data to the bus the RAI l s a re w r i t ing to the bus R W 0 is low w r i t e ROM Th i s memo r y i s comp r i s e d o f two 1 6K x 8 ma s k e d ROM ch ip s I t cont a ins the BAS IC i ...

Страница 79: ...gh re l iab i l i t y The 486 4 us es a s i ng l e t r ans i s t o r dynam ic st ora ge ce l t and a dvanced dynam ic c i rc u i t r y th roughou t inc l uding t he 512 s ense amp l i f ie rs wh ich a s sures tha t power di s s ipa t ion i s min i m i z e d Re f resh charac t e r i s t i c s have been chosen to max i m ize y ie ld low cost to us e r wh i l e ma i n t a i n ing compa t ib i l it y ...

Страница 80: ...e Genera tor 0 A Conve rters produce the ba s ic s qu a re wave tone f re quenc i e s for each cha nne l A B C p roduce a f re quency modu l a ted p s e udo random pu l se w i d th squa re wave ou tpu t comb i ne the ou t pu t s of the Tone Gene rators and the Noise Genera t o r One for each channe l A B C p rov ides the D A connectors w i th e i t her a f ixed or va ri able amp l i t ud e pa t t ...

Страница 81: ...c t i on w i th a ddre s s inputs A9 and A 8 f o rm t he h i gh o r d e r address ch ip se l ec t AB i nput pin 25 A9 i npu t p i n 24 A dd r e ss 9 Address 8 The s e ex tra add re s s b i t s are ma de ava i l a b l e to enab l e the pos i t i o n i ng of the PSG a s sign ing a 16 word memory space in a t o t a l 1 024 word memory a rea rather than in a 256 wor d memor y area as d e f i n e d by ...

Страница 82: ...ANALOG CHANNEL A B C ou tput Each o f these s i gna l s i s th e ou tput of i t s corre sponding mix of T4 and p rovides an up to 1V peak peak s ignal rep resent ing the comp l ex sound wave shape gene ra t e d by the PSG I OA 7 IOAO inpu t output I OB 7 IOBO inpu t outpu t Inpu t O u tput A7 AO B7 BO pins 1 4 2 1 p ins 6 13 Eac h of these two paral l e l inpu t output por t s p rovides 8 b i t s ...

Страница 83: ...bank con t r o l signa l s for t he memory ch i ps De t a i l signa l s for the ports a re l i s t e d in the t ab l e be l ow AY 3 81 90 I 0 Port A DO D1 D2 D3 D4 DS D6 D 7 Joy s t ick do do do J oy s t ick do do do 1 2 AY 3 8910 I 0 Port B DO Bank 1 Game D 1 Bank 2 1 D2 Bank 2 2 D3 Bank 3 1 D4 Bank 32 Inpu t Por t 1 No Contact 0 Forward 0 Backwa r d 0 Le f t 0 R ight 0 Forward 0 Backwar d 0 Le f...

Страница 84: ...i ona l conf igura t ion of the 82 55A is p rogramme d by the system sof tware so that normal ly no ex t e rnal log ic i s nec e s sary to interf ace p e r iphe ra l devices or s t ruc t ures Da t a Bus Buf fer Th is 3 s t ate b i d i rect i ona l 8 b i t buf f e r i s use d to int e r f ace the 82 55A to the s y s t em da ta b us Data i s transm i t te d or rece ive d by the buffer upon execu t i...

Страница 85: ...ree ports or the cont ro l wor d reg i s ters They are norma l ly connected to the l eas t s ignif icant b i t s of t he a ddre ss bus Ao and A1 8 2 55A BAS IC OPERATION A Ai RD WR cs INPUT OPERATION READ 0 0 0 1 0 PORT A DATA BUS 0 1 0 1 0 PORT B 7 DATA BUS 1 0 0 1 0 PORT c DATA BUS OUTPUT OPERATION WRITE 0 0 1 0 0 DATA BUS PORT A 0 1 1 0 0 DATA BUS PORT B 1 0 1 0 0 DATA BUS PORT c 1 1 1 0 0 DATA...

Страница 86: ... 5 5A cont a ins three 8 b i t por t s A B and C Al l can be conf igured in a w ide var i e t y of func t iona l charac t e r i s t i cs by t he s y s t em software but e ach has it s own spec ia l fea ture s or pe rsona l i ty to fu rthe r enhance the powe r and f l ex i b i l i t y of t he 8 2 55A Por t A One 8 b i t data ou tput lat ch buf f e r and one 8 b i t dat a input l a t c h Port B One ...

Страница 87: ... e te devi ce ope ra t i on a s imp l e log ical I 0 approach w i l l s u r f ac e The des ign of the 8 2 55A has taken into account th ing s such as e f f i c ient PC board layou t cont r o l s igna l de f i n i t ion vs PC la yout and comp l e t e func t i ona l f l ex i b i l i t y to supp o r t a lmos t any per iphera l dev i ce w i th no ext e rn a l log ic S uch des ign represents the max im...

Страница 88: ...te Ready 0 Ready 1 not ready D7 Ca s s e t t e Read Data 8 2 5 5 Por t B Input Port DO D7 Keyboard Read Data 8 2 55 Port C Output Port DO D3 D4 D5 D6 D7 Keyboard BCD Output Da ta For Keyboa rd Scann ing Ca s s e t te Motor On 0 Motor On 1 Motor O f f Ca s se t te Wr i t e Data Ca s se t t e Aud i o Cont rol 1 Enab l e other channe l in 0 D i sab l e other channe l in Mix PSG S ound Da ta 8 2 55 Co...

Страница 89: ... ta Ou t put S t robe DOSTR DOSTR P i ns 1 9 and 1 8 When DOSTR is h igh or DOSTR i s l ow wh i l e the ch ip is se l ec t e d a l l ows the CPU to w r i t e data or cont r o l words i n t o a se l ected reg i st er of t he INS8 2 50 Not e Only an act ive OOSTR o r OOSTR input i s re quired to t rans fer data to t he INS8 250 du r i sng a wri t e ope ra t ion There fore t ie e ither the DOSTR inpu...

Страница 90: ...OUT 2 RTS DTR a re a ffected by an active MR input Re f er to tab le 1 Rece i ve r C l ock RCLK P in 9 Th i s input is the 1 6x baud ra te c lock for the rece iver sec t i on of the ch ip Ser ia l Input SI N Pin 1 0 Ser i a l data input f rom the communicat ions l ink pe r iphe ral dev ice MODEM or data s et C l e a r to Send CTS Pin 36 The CTS s igna l is a MODEM con t ro l funct ion input who se...

Страница 91: ...ra ted if the MODEM S t a t us Interrupt is enab led R ing Indicator RI P in 39 When low indicates that a te l ephone r inging s i gna l ha s been received by the MODEM or data se t The R I s igna l i s a MODEM con t rol func t i on input who se cond i t i on can be t e s ted by the CPU by rea ding b i t 6 R I of the MODEM Sta tus Reg is ter B i t 2 TERI o f the MODEM S tatus Register indica t es ...

Страница 92: ...tput t o t h e RCLK input o f t h e chip Int e rrupt INTRPT P in 3 0 Goes h i gh whenever any one of the fo l low ing inte r rup t t yp e s ha s an ac t i ve high cond i t i on and is enab l ed via the IER Re ce iver E rror F lag Rece iver Data Ava i l ab le Transm i t ter H o l d ing Reg i s te r Empt y and MODEM S ta tus The INTRPT s i gna l is re set low upon t h e approp riate inte rrupt se rv...

Страница 93: ...n detected by the rece i ver as a logic 0 if b i t 4 i s a logic 1 or as a log ic 1 i f b i t 4 a l ogic 0 Bit 6 This b i t i s the Set Break Control b i t When b i t 6 i s a log ic 1 the se ria l output SOUT is forced to the Spac ing logic 0 state and rema ins the re reg a r d l e s s of other t ransm i tt er activity The s e t b reak i s di sab led by s e t ting b i t 6 to a log ic 0 Th i s feat...

Страница 94: ... receer Data Ready DR indicator Bit 0 is set to a log ic 1 whenever a comple te incoming character has been rece ived and trans ferred into the Receiver Buffer Register Bit 0 may be reset to a logic 0 either by the CPU reading the dat in the Receiver Buffer Register or by wr it ing a logic 0 into it from the CPU Bit 1 This bit is the Overrun Error OE indicator Bit 1 indicates that data in the Rece...

Страница 95: ... l ab l e B i t 0 DTR I n t e r r up t WLSO E RBFI D a t a B i t 1 E na b l e I n t e r r up t Wor d R e qu e s t T r a n sm i t I D B i t Leng th t o S end t e r H o l d i ng 0 S e l e c t RTS R eg i s t e r B i t 1 Empt y WLS 1 I n t e r r u p t ET B E I Da t a B i t 2 E na b l e I n t e r r upt Numb e r Out 1 R e c e i v e r I D B i t of S t op L i ne 1 B i t s S t a t u s S T B I n t e r r u p...

Страница 96: ... i gna l D e t e c t DRL S D E v e n Loop B reak C l e a r B i t 4 P a r i t y I n t e r to S e n d S e l e c t r u p t CTS EP S B I S t i ck 0 T r a n s D a t a S e t B i t 5 P a r i t y m i t t e r Rea dy H o l d ing DS R Re g i s t e r Emp t y TS R E S e t 0 T r a n s R ing B i t 6 B re a k m i t t e r I n d i Sh i f t c a t o r Re g i s t e r R I Emp t y TS R E D i v i s o r 0 0 R e c e i ve d...

Страница 97: ...2 1 200 96 1800 64 2000 58 2400 48 3 600 3 2 4800 24 7 2 00 16 9600 1 2 1 9 2 00 6 38400 3 56000 I 2 T ab l e 3 B a ud Ra t e s U s ing 1 8432 MHz C r y s t a l Percent E r ror D iff e re nce between De s i re d Actual 0 02 6 0 058 0 69 2 86 N o t e 1 843 2 MHz i s t h e s t an d a r d 8080 f re quency d i v i d e d b y 1 0 6 64 ...

Страница 98: ...1 0 1 7 45 1 34 5 1 42 8 1 50 1 2 80 300 640 600 3 20 1 200 1 60 1800 1 07 2000 96 2400 80 3600 53 4800 40 7200 27 9600 20 1 92 00 1 0 38400 5 Tab l e 4 Baud Ra tes Us ing 3 072 MHz Crys t a l 6 65 P re sent Error D i f f e rent Between De s i red and Act u a l 0 026 0 034 0 3 1 2 0 62 8 1 23 ...

Страница 99: ...data term ina l emp l o y ing a cu rre nt i n t e r face t he da ta t e rm i n a l MUST be s e t up to ope rate in the Ful l Dup l e x 20 M i l l iampe r e Neut r a l con f i g u ra t i o n Re f e r to the re l a t e d e qu ipment manual f o r i n s t r u c t ions TERMINAL Inter face P in Ass ignments EIA RS 23 2 C P in 1 2 3 5 6 7 8 20 1 6 25 Func t i on P ro tect ive Ground Transm i t t e d Da t...

Страница 100: ...y Output R dy OV Busy 5V S t a r t S top Inpu t S t a r t OV S t op 5V 1 6 and 25 a re o p t i onal features The Hodem CPU in t e r face ca b l e and connector conform to EIA RS 232 C and Eu rope an CCITT V 24 s t andards and is a 2 5 p in DB 25P conne c t or The ma t i ng connector loca t e d connector loca t e d on the dataset or acoust i c coup le r shou ld be a DB 25S o r e qua l S igna l s to...

Страница 101: ... by rea d ing writ ing into t he 18 reg i s ter f i l e of t he CRTC The Re fre sh Memory add re s s is mul t i p l exe d be tween the P roce ssor and CRTC Data appea r s on a Secondary Bus wh ich i s buffered f rom the p roce s sor Pr imary Bus A number of approache s are poss i b l e for solv ing onten t i ons for the Re f resh Memory 1 Proce s sor a l ways ge t s p r i or i t y 2 Proce s sor g ...

Страница 102: ...1 6 ra s t e r l ine s i n the ve rt ica l con t ro l sect i on and i s not p rogrammab l e 2 Ve r t ical D i sp lay of a f re quency and po s i t i on determ ined by the re g is ters The Ve rt i c a l Contro l Log ic has othe r func t ions 1 Gene ra te row se lects RAO RA4 f rom t he Ras ter Count for the corresponding in t e r lace or non inter lace modes 2 Extend the number of scan l ine s in t...

Страница 103: ...t to the reference Hor i zontal Total Reg ister RO Horizont al Disp layed Reg ister Rl Horizontal Sync Pos ition Reg ister R2 Horizonta l Sync Width Reg ister R3 This 8 bit write only register determines the hor izontal f requency of HS It is the total of di splayed plus non displayed character t ime un its minus one This 8 bit write only register determines the number of displayed characters per ...

Страница 104: ...on is p rogrammed in the 5 b it wr i te only Vert ica l Scan Ad j ust Reg ister as a number of scan l ine t imes This 7 bit write on l y reg ister dete rmine s the number of disp layed charac te r rows on the CRT screen and is programmed in character row t imes This 7 bit wri te on l y reg ister determine s the ve r t ical sync pos i t ion with respect t o the re ference I t is programme d in cha ...

Страница 105: ...bit read only reg ister is used to store the contents of the Address Register H L when the LPSTB input pul ses high This reg ister cons ists of an 8 bit lower and 6 bit higher register This 14 bit read write register stores the cursor location This register consists of an 8 bit lower and 6 bit higher register The Cursor Sta rt and End Registers al low a cursor of up to 32 scan l ines in height to ...

Страница 106: ... l ace Sync and Video Th is last mode e ff ect ive ly doub l es the charact e r dens i t y on a mon i t or of a g iven bandwidth The d i sa dvantage of both inte r lace modes i s an appa rent fl icker e ff ec t wh ich can be re duced by ca re ful mon i t or de s ign The re are re s t r i c t i ons on the porgramm ing of CRTC registers for inte r lace ope r a t i on 1 Hor i zont a l total cha rac t...

Страница 107: ... l i ng up or down is pos s ib le by l i ne page or cha racte r The CRTC inter faces t o a p roce s sor b u s on the b i d i rec t i ona l data bus DO D7 us ing CS RS E and R W for con t ro l s igna l s Dat a Bus DO D7 Ena b l e E Chip S e lect C S The b id i re c t iona l d a t a l i nes DO D7 a l l ow d a ta t rans f e rs between t he CRTC inte rna l Reg i s t e r F i l e and the p roce s sor Da...

Страница 108: ... b l e output i s an ac t ive h i gh s i g n a l w h ich d r ives the mon i tor d i rec t l y or i s f e d to V i d e o P roc e s s ing Log i c f o r c omp o s i te g e n e r a t ion Th i s s ig na l d e t e rm i n e s t he ho r i z ont a l pos i t ion of t he d i s p l a y e d t ex t Th is TTL compa t i b l e ou tput is an ac t ive h i gh s ig n a l wh ich i n d i c a t e s the CRTC i s p rov i d...

Страница 109: ...ch ing i s on the low to h igh edge and is synchron ized inte rna l ly to cha rac t e r c l ock The RES input is used to Reset the CRTC An input low l eve l on RES fo rces CRTC into fo l low ing s t atus A A l l the count e r s in CRTC are c l eared and the dev i ce s tops the disp lay ope ra t ion B Al l the ou tpu t s go down to low l eve l C Control reg i s t e rs in CRTC are not a f f ec t e d...

Страница 110: ...4 77 C The CRTC s t a r t s the D i s p l ay ope ra t ion i mme d ia t e ly a f te r the re l ease o f RES s igna 1 RES LPSTB OPERATING HODE 0 0 Rese t 0 1 Te s t Node 1 0 Norma l Mode 1 1 Norma l Mode ...

Страница 111: ...t H 1 t t H t CUfiSOR CONTROL I I On Off On I I I I Blink Period r 16 or 32 Tlmn I flold Period o t H o t H FIG 4 7 3 H H H 5 t t H t 2 l t t HI 3 H 4 l t t Hr 1 H t t t t t H F IG 4 8 Bit Bit 1 0 0 0 1 0 0 1 1 1 Sufi LIM AdcllreM 0 e e 3 e 1 t t t t t 1 t t t t H H o t H 1 1 t hH Cur101 Start Adt I Curoor End Adr t Modo Normol Sync Modo INon lntorlocol lntlfiKO Sync Modo lntoriKo Sync a Vldoo Mod...

Страница 112: ...d re s s R eg i s t e r RO H o r i z on t a l Cha r To t a l R 1 H o r i z on t a l C h a r D i s p l aye d R2 H SYnc C ha r P o s i t i on RJ H Sync W i a th C h a r R4 Ve r t i c a l T o t a l C h a r Row R S V T o t a l S can L i ne Ad j u s t R6 V e r t i c a l C h a r Row D i s p l a y e d R 7 v S y nc C h r Row Pos i l i o n R8 I n t e r l a c e 1 o d C R e a d Wr i t e No Ye s N o Y e s N o...

Страница 113: ...s 1 1 0 0 R 1 2 S t a r t No Ye s Add re s s H 1 1 0 1 R 1 3 S t a r t No Y e s A dd r e s s L 1 1 1 0 R 1 4 Cu r s o r H Y e s Y e s 1 1 1 1 R 1 5 Cu r s o r L Y e s Y e s 0 0 0 0 R 1 6 L i gh t P e n H Y e s N o 0 0 0 1 R 1 7 L i gh t P e n L Y e s N o B i t 5 o f t h e Cu r s o r S t a r t R e g i s t e r i s us e d f o r b l ink pe r i od con t r o l a n d B i t 6 i s u s e d t o s e l e c t b...

Страница 114: ...ped in towards track 7 6 and decremented by one when the head is stepped out towards track 00 The contents of t he reg i ster are compared with the recorded track number in the ID fie l d du ring disk Rea d Wr ite and Ve rify ope r a t ions The Track Reg i s ter can be l oaded f rom or t rans f e rred to the DAL Th i s Reg is ter shou ld no t be loaded whe n the device is bus y SECTOR REGISTER SR ...

Страница 115: ... i s log ic l ow the command i s not exec uted and an interrup t is gene ra ted A l l type I commands are per forme d reg ar d l e s s o f t he sta te o f the keady input A l so whenever a Type II or III command i rece ive d the TG43 s igna l ou tput i s update d PROCE SSOR INTERFACE The int erface to the p roce ssor i s accomp l i shed th rough the e i ght Data Acce ss L i nes DAL and a s sociate...

Страница 116: ...TRQ is res e t by e i ther reading the status reg i s t e r or by l oa d ing the command reg is ter with a new conunand In addi t i on INTRQ is generated if a Force inte rrupt command c ond i t i on is met FLOPPY DISK INTERFACE The 1 793 ha s two modes of ope rat ion according to the state of DDEN Pin 3 7 When D DEN 1 s ing le dens ity i s se l ecte d In either ca se the CLK input P in 24 is at 2 ...

Страница 117: ...T and HLD a r e T rue b S e t t ing Time if p rogramme d has exp ire d c th e 1793 i s inspec t i ng d a t a of f the d i sk I f WF VFOE is no t used l eave open or t i e to a lOK res i s t o r to 5 D I S K WR ITE OPERAT ION Whe n wr i t i ng is to take p l a ce on the d i sket t e the Write Ga te WG ou tpu t i s ac t i va te d a l low ing cu rrent t o f l ow i n to the Read Wh i te hea d As a pre...

Страница 118: ...t e p recompensat i on s igna l s EARLY and LATE a re val i d for t he du ra t i on of WD in both FM and Mfll f orma t s WR ITE RECOMPENSAT ION Wr i t e p re compe n s a t i o n wh ich coun t e rac t s th e d r i f t ing when f l ux t rans i t ions a re p la ced c lo s e toge ther on t he more c r ampe d ins ide t racks is ava i l ab l e to the user on any t rack s tha t he fee l s nec e s s a ry ...

Страница 119: ...d ica tes the hea d i s loaded and engaged Th i s I b i t i s a log ical and of HLD and HLT s igna l s I 54 5 EEK ERROR When se t t he d e s i red t rack was not ve r i f ie d Th i s b i t i s re set to 0 when updat e d 5 3 C RC ERROR CRC encoun tered in ID f i e l d 5 2 TRACK 00 When s e t ind icates R ead Wr i te head is pos i t i oned to Track o Th i s b i t is an inve r t e d copy o f the TROO...

Страница 120: ...a ta Mark 0 Data Mark On any Wr i te I t indica tes a Wr ite Fau l t Th is bit i s re s e t whe n updated S4 RECORD NOT When se t it ind icates that the d e s i red t rack sector or FOUND RNF side we re not found Th is bit is re s e t when update d S3 CRC ERROR I f S4 i s se t an e r ror i s found in one or more ID fie lds ot herw i se it indicates e r ror in data f i e ld Th is b i t i s re s e t...

Страница 121: ...che d in the disc An add i t i ona l ho l e INDEX oc curs app roximate ly 180 degrees be fore sec tor 0 se c t or locat ion depen d s upon the re lat ive po s i t ion of the rea d wri te head and the index sensor Each track s ta r t s with a p u l se init ia ted by the Index hole wh i l e each sector s t a r t s by a pu l s e in i t ia t e d by a sec tor hol e Notice tha t the phy s ic a l l ength...

Страница 122: ... ve S e l ec t i on Drive se l ec t i on occurs when the app ropriate DRIVE SELECT l ine is act ivated and t he p roper se lect j umpe r b l ock is insta l l e d Mot or On In or der for the ho st system to read or wri t e data the de dr ive motor mus t be tu rne d on Th i s is accomp l i shed by act iva t ing the MOTOR ON l ine A 350 ms de l a y mus t be introduced after act iva t ing th i s l i n...

Страница 123: ...g e dge of the s t ep pu lse Head movement is in i t iated on the t ra i l ing e dge of t he s t ep pulse S t ep Out With the DIRECTION SELECT line at a log ica l one leve l 2 5 to 5 2SV a pulse on t he STEP l i ne wi l l cause the read wri te head to move ei ther one t rack away f rom th e centre of the di sk towards track 00 S tep In With the DIRECTION SELECT line at a m inus logic leve l 0 to 0...

Страница 124: ...RE Command is execute d regar d l e ss o f the s tate o f the Re dy signa l from the drive A l so HEX 0 1 is loa ded into sec tor reg ister Ground 5V 5 1 2V 5 A log ic low on th is input gates data on th e DAL into the se l ected register when CS is low A logic low on th is input se lects the chip and enab les computer communi cat ion with the device A log ic low on th is input cont ro l s the p l...

Страница 125: ...ading or loading the DR in Read or Wr ite operat ions respec tive l y Use 10K pul l up resistor to 5 39 INTERRUPT REQUEST FLOPPY DISK INTERFACE 1 5 STEP 16 DIRECTION 1 7 EARLY 18 LATE INTRQ STEP DIRC EARLY LATE 4 92 This open drain output is set at the complet ion of any command and is reset when the STATUS register is read or the command register is written to Use 10K pul l up resistor to 5 The s...

Страница 126: ...de Se l ct Output i s d i r ec t l y con t ro l l e d b t S f l ag in Type I I or I I I comm nds Whe n S 1 SSO i s set t o a log c 1 Wh en S O SSO i s s e t to a log c 0 The S ide S e l ec t Outpu t i s onl y upd a ted a t the beg inn ing o f a Type 1 or I I I command I t i s forced t a log ic 0 up on a HASTER RESET con d i t ion A nom i nal s quare wave c l ock s igna l der ive d from the data s ...

Страница 127: ...The Ready input appea rs in inve rted format as S tatus Reg ister b id 7 Th is is a b id i rect i ona l s ignal use d to s ign i fy wr i t ing fau l ts at the drive and to enab l e the externa l PLD data separator When WG 1 P in 33 func t ions as a VFOE output VFOE will go low dur ing a read ope rat ion a f ter the hea d has loaded and set t led HLT 1 On the 1 795 7 it w i l l remain l ow unt i l ...

Страница 128: ...rece ived A log ic low term i n a t e s the command and set s chc I W r i t e P ro t ect S t a t us b i t Th i s p in se l e c t s e i ther s ingl e or dou b l e den s i t y opera t ion When llDEt oub l e dens i t y i s se l ec t e d Hhen DDEN 1 s ing le dens i t y is se l e c te d Th i s l i ne mus t be l e f t open on the II I 1 7 9 2 4 i _I ...

Страница 129: ...ND PAIR WITH 3 PIN DATA 3 22 TW ISTED PAIR GND PAIR WITH 4 PIN DATA 4 23 TWISTED PAIR GND PAIR WITH 5 PIN DATA 5 24 TW ISTED PAIR GND PAIR WITH 6 PIN DATA 6 25 TWISTED PAIR GND PAIR WITH 7 P IN DATA 7 26 TWISTED PAIR GND PAIR WITH 8 PIN DATA 8 27 TWISTED PAIR GND PAIR WITH 9 PIN ACK 28 TWISTED PAIR GND PAIR WITH 10 PIN BUSY 29 TWISTED PAI R GND PAIR WITH 1 1 PIN GND 30 GND NC 3 1 IN ITIAL PAIR WIT...

Страница 130: ...int ing test which is executed by bring ing the l ine LOW 2 Output signa l s f rom t he P r in t er BUSY Th i s s igna l indica t e s the BUSY status of the Print e r When HIGH t he Print er cannot accept data ACK Th is s igna l i s used to ind icate that the Printer i s awa i t ing da ta Not e The BUSY and ACK s igna l s are a lways outpu t when the Printer accep ts da ta input ERROR A printer e ...

Страница 131: ...d Tr 1 00 ns or l e s s T va l ue shown on the t iming chart Input output s i gna l s are pu l l e d up with 10 k ohms Input s igna l s The input load cor respond s to one 74LS04 Output signa l s The out p ut corre sponds to a 74LS04 The recommended output l oa d corre spond s to one LSTTL l oa d S V t oo n t ok n r Input llOOOpF _ t _ These are attached only 74LS04 equivalent to the INITIAL and S...

Страница 132: ...iming Cha r t 1 Da ta input DATA 1 8 _L _ l _ _ _ ___ 0 us min 1 14 1 0 us min I L s T RO BE u u 0 0 5 us _ t l O 00 us __ 1 0 us min r BUSY 4__ __ T _ b _ _ __ ACK Tb CHARACTER CODE CR NL DC4 CODE u I I 5 I O us 100 s or more PRINTER CARRIAGE RETURN about 3 econds max imum Reference CR o D NL 0 A DC4 1 4 2 INITIAL s igna l inpu t t im ing INITIAL BUSY J ACK 4 99 MAX about 2sec ss bJ ...

Страница 133: ...K s igna l 5 S e l f Te st P r int ing 500 600 ns r r I 2 5 J LS f 400 KHz Bringing the TEST l i ne LOW starts the se l f test p rint ing wh ich cont inues unt i l i t is retu rne d HIGH 6 Cha s i s Ground As stated in 6 3 3 al l of the signa l l ine s shoul d be twisted p a i rs with t he s ignal ground l ines but it is further recommended that the cab l e be sh ie lded and tha t one term ina l b...

Страница 134: ...5 CIRCUIT SCHEMATIC AND COMPONENT LAYOUT 5 1 ...

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