XAV-AX200/AX200C2
XAV-AX200/AX200C2
41
41
5-18. SCHEMATIC DIAGRAM - TFT Board (2/8) (XAV-AX200) -
TFT VGL & VGH & AVDD_10V4
TFT Back light
0.3mA
02',)<
$''
1
GND
2
OU
T
3
IN
U3
1117-3.3A
C5
10uF
1
SW
2
GND
3
FB
4
EN
5
OV
6
IN
8
,&03
C44
10uF
DV3V3
C41
10pF
FB2
)%5
FB1
)%5
FB3
)%5
C10
104
R10
1K
R1
7
47K
D3
16V
C36
1uF
C40
1uF
R18
560R
R2
0
220K
D5
6V8
C49
10uF
C46
104
C47
D4
1N5819
C53
104
C66
103
1
2
3
Q4
BAV99
L1
2.7uH
L2
10uH
C69
NC
L3
10uH
R14
1K
R3
2
47K
D6
1N5819
L4
10uH
R33
4K7
R34
82K
R3
6
1R
3/1%
R3
7
1R
3/1%
R3
8
NC
C125
10uF
C126
104
C11
10uF
C143
10uF/25V
C42
10uF
L8
X+
C147
NC
C50
10uF
C51
10uF
C52
10uF
C54
10u
F
C55
10u
F
R91
0R
R9
2
.
R9
3
120K/1%
R9
4
10K
R9
5
240K/1%
R9
6
11K/1%
R98
0R
1
GND
2
OU
T
3
IN
U7
1117-3.3A
C157
10uF
C160
104
C161
10uF
R31
FB
TP2
TP3
TP5
TP6
TP7
TP9
TP10
TP11
TP12
TP13
C15
104
C16
2.2uF
FB12
)%5
1
SW
2
GND
3
FB
4
EN
5
IN
8
03
1
GND
2
OU
T
3
IN
U12
1117-Adj
FB9
)%5
FB11
)%5
C25
10uF
C103
10uF
C20
10uF
C23
10uF
TP19
C22
104
C153
104
C75
104
C78
222
J11
J12
C3
104
C4
104
C70
9
C43
104
C149
104
C148
3
C74
C19
104
R121
0R
C195
104
FB25
)%5
TP31
C223
104
C95
104
R3
9
5
R40
5
D13
C45
22uF
C216
10uF
C293
10uF
C73
10uF
C239
10uF
C76
10uF
C77
10uF
L15
X+
C135
10uF
C325
NC
C326
NC
TP38
C327
104
1
GND
2
OUT
3
IN
U19
1&
R275
0R
R277
1&
R279
1&
J5
J6
FB4
)%5
C346
10u
F
C347
10u
F
C348
10u
F
R311
1&
C170
NC
C190
NC
C214
NC
C231
NC
C274
NC
C349
NC
1
2
3
4
5
PD
1
1
2
3
4
5
PD
2
1
2
3
4
5
PD
3
1
2
3
4
5
PD
4
1
2
3
4
5
PD
5
1
2
3
4
5
PD
6
1
2
3
4
5
PD
7
1
2
3
4
5
PD
8
1
2
3
4
5
PD
9
1
2
3
4
5
PD
10
1
2
3
4
5
PD
11
1
2
3
4
5
PD
12
C366
NC
C384
NC
C360
1uF
1
2
3
Q2
BAV99
1
2
3
4
5
PD
13
1
2
3
4
5
PD
14
1
2
3
4
5
PD
15
1
2
3
4
5
PD
16
R353
0R
[1] MCU_BL_CTL
GND
BL_GND
>@
7)7B9
[1]
VLED+
[1]
VLED-
BL_GND
BL_GND
BL_GND
HL_GND
HL_GND
HL
_G
N
D
HL_GND
HL_GND
HL_GND
[1]
AVDD_10V4
[1]
VGL_-7V
[2]
VM1
[2]
VM1
[1]
VGH_16V
BL_GND
BL_GND
BL
_GND
>@
7)7B9
[1,2,8]
PWR_3V3
GND
[1,2,8]
PWR_3V3
[1]
DVDD_3V3
[6]
CP_3V3
[8]
BT_3V3
[5]
MLV_3V3
>@
7)7B9
>@
7)7B9
[6,7]
AK_VDD_3V3
[6]
SGM_3V3
[2]
MLV_1V5
[2]
MLV_1V5
DGND
[5]
A_1V5
[1,2,8]
PWR_3V3
[5]
C_1V5
[6]
BL_ADJ
[5]
MLV_D_3V3
DGND
[6]
CORE_BL_CTL
>@
7)7B9
LDO_4V
>@
.(<B%/B9
HL_GND
ASP_GND
ASP_GND
ASP_GND
A
E
D
B
C
1
2
3
4
5
6
7
8
9
(2/8)
TFT BOARD
F
SYS SET
2018/04/20 05:09:38 (GMT+09:00)