45
STR-DA7100ES
Pin No.
Pin Name
I/O
Description
60
RESET_ARM
I
System reset signal input from the i. link system controller “L”: reset
61
LINK_ON
-
Not used
62
HPS
-
Not used
63
LOW_PWR_RDY
-
Not used
64
DISABLE_IF
-
Not used
65
GPIO0
O
Reload timer output to the main system controller
66
GPIO1
O
Clock mode switch signal output terminal
67
SDA
-
Not used
68
SCL
-
Not used
69
GPIO6
O
FSSEL signal output to the i. link DSP
70
GPIO7
O
Data receive start signal and reset signal output to the i. link DSP
71
GPIO8
O
SA-CD channel select signal output to the i. link DSP
72
GPIO9
I
FSTATE signal input from the i. link DSP
73
REG_EN
-
Not used
74
REG_OUT
-
Not used
75
VDD
-
Power supply terminal (+3.3V)
76
VSS
-
Ground terminal
77
TMS
-
Not used
78
TDI
-
Not used
79
TDO
-
Not used
80
TCK
-
Not used
81
TRST
-
Not used
82
ARM_TMS
-
Not used
83
ARM_TDI
-
Not used
84
ARM_TDO
-
Not used
85
UART_TXD
-
Not used
86
UART_RXD
-
Not used
87
GPIO10
I
FSTATE signal input from the i. link DSP
88
TMR WTCHDOG
-
Not used
89
MCIF_INT
O
Interrupt request signal output to the i. link system controller
90
MCIF_CS_IO
I
Chip select signal input from the i. link system controller
91
MCIF_CS_MEM
I
Chip select signal input from the i. link system controller
92
MCIF_R_NW
-
Not used
93
MCIF_STRB
-
Not used
94
MCIF_WAIT
O
Bus wait request signal output to the i. link system controller
95
MCIF_ACK
-
Not used
96
MCIF_OE
I
Read data input from the i. link system controller
97
MCIF_WE
I
Read/write enable signal input from the i. link system controller
98
MCIF_BUSCLK
I
Serial data transfer clock signal input from the i. link system controller
99, 100
MCIF_DATA0,
I/O
Two-way data bus with the i. link system controller and flash memory
MCIF_DATA1
101
VDD
-
Power supply terminal (+3.3V)
102
VSS
-
Ground terminal
103 to 114
MCIF_DATA2 to
I/O
Two-way data bus with the i. link system controller and flash memory
MCIF_DATA13
115
REG_OUT
-
Not used
116
VDD
-
Power supply terminal (+3.3V)
117
VSS
-
Ground terminal
