Sony HVR-M10C, Руководство по обслуживанию

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HVR-M10C/M10E/M10J/M10N/M10P/M10U
3-1 3-2
3-1. OVERALL BLOCK DIAGRAM (1/5)
3. BLOCK DIAGRAMS
( ) : Number in parenthesis ( ) indicates the division number of schematic diagram where the component is located.
RYO0-RYO3,DEHD,DEVD,DEFLD,SGOUT
RCO0-RCO3,EDHD,EDVD,EDFLD,FRMREF
RYI0-RYI3,DE0-DE3
RCI0-RCI3,DE4-DE7
IC2021
132
24
17
193
423
186
332
189
111
17
419
BASE BAND
PROCESS
26-29
264-267
30-38
273-276
222-234
442-452
8-15
245-252
107-110
339-342
55,54
102-105
334-338
45,46
283,285
43,44
281,282
53,290
291,292
51,52
288,289
257
•
258
•
19
262
•
25
•
263
315
•
85
•
317
115
•
344
418
•
197
419
•
201
254
255
A2-A19
D0-D15
SPCKO
VFI HD
VFI VD
VFI OE
COLH1
COLH2
COLH3
AFCK
CK13MFO
CK14MFO
Y
PR
PB
Q2119-2121
Q2110-2112
HOSDHD
HOSDVD
VFIY0-VFIY7
VFIC0-VFIC7
IC5001
IC2022
VIDEO
A/D
CONV.
IC2023
VCO
(1/16)
IC2101
OSD
59
|
52
49
|
42
38
•
37
•
36
17
•
16
•
14
64
•
66
•
63
2
6
25
34
8
68
20
•
19
3
•
1
313
•
80
81
LPF
EVGR
EVBL
XPHD
XPVD
Q2116-2117
BUFF
PLRE
PLGR
PLBL
YO
PRO
PBO
EVGR
EVBL
XPHD
XPVD
PLRE
PLGR
PLBL
Q2113-2115
BUFF
75
•
79
•
77
72
•
74
68
•
69
•
67
64
•
56
IC8003
16Mbit
SDRAM
IC8001
FLASH
MEMORY
IC8009
DS
CONTROL
IC3001
HDV
VIDEO
DECORDER
IC4001
DV
SIGNAL
PROCESS
RF
SIGNAL
PROCESS
IC7001
HDV
AUDIO
SIGNAL
PROCESS
IC8601
LSI
CONTROL
IC2502
HDV
SIGNAL
PROCESS
HDV
RF SIGNAL
PROCESS
IC3501
iLINK
INTERFACE
59
|
52
241
|
251
187
|
197
77
|
85
139
|
136
95
|
98
226
291
252
143 86
30
45
41
71
72
276
279
277
281
73
74
80
82
1
3
139
104
59
35
60
47
21
97
45
74
78
15
CK27MFO1
FLD27MF FLD27MF
CK27MFO1
CK DENEBO2
VCK
ADATAIN0
ADATAIN1
CK64FSO
CK13MFO CK13MFO
CKFSO CKFSO
CK64FSO
CKFSO
DSCK VM
ADATAOUT0
ADATAOUT1
DHD
DFD
A0-A10
D0-D31
A0-A10
D0-D31
IC3201
Y SDRAM
IC3202
C SDRAM
287
•
286
168
•
127
167
•
126
204
•
203
42,44
47-49
52-55
61,64
66
3-24
33-35
58,59
61
68-90
123-124
134-137
144-147
151
92-118
148,150
155-176
22,20
119
•
162
•
120
•
163
70
•
121
•
71
•
122
13
•
72
•
14
•
73
60
•
58
•
112
•
111
149
•
186
•
150
•
187
123
•
166
•
124
•
125
187,188
54
•
152
•
55
•
190
•
155
107
•
189
•
153
•
109
•
192
114
•
157
•
3
66
•
65
•
63
38,42
48,49
62,18
39,46
58,69
81,95
120,124
135,6
43,73
41,71
195,198
ADATAIN0
AUIN21 AUIN21
FRRV
TRRT
CK64FSO
DSCK VM
(1/2)
20-26
29-35 20-26
29-35
16-35
123
124
D0-D15
A1-A22
D0-D15 A1-A21
D0-D15 A1-A14
A1-A22
D0-D15
CKFSO
DSCK VM
AUIN11
ADAO1
CK64FSO
CKFSO
CK256FSO
TO
OVERALL
BLOCK DIAGRAM
(2/5)
6
Y
Y
C
C
CK
CK
TO
OVERALL
BLOCK DIAGRAM
(2/5)
2
TO
OVERALL
BLOCK DIAGRAM
(3/5)
1
DJCLK
RF IN RF IN
SWP
FRRV
TRRT
TRRV SWP
FRRV
TRRT
TRRV
DJCLK
VIT DT
VIT CK
CREC DT
CREC CK
VIT DT
VIT CK
CREC DT
CREC CK
185 87
7
1
10
HDAT[0]-HDAT[7]
215
225
223
221
220
231
227
224
191,218
193-201
204-207
210-213
179-189
192
AUDAL
AUDAO
AUENI
AUENO
AUDAO
AUENI
AUENO
AUDAL
X8601
20MHz
HADR[0]-HADR[7]
HADR[0]-HADR[3] HADR[0]-HADR[13]
44-37
33-28
HDAT[0]-HDAT[7] HDAT[0]-HDAT[7]
52
|
45
AUIN21
256
|
266
HDAT[0]-HDAT[7]
PD10-PD17
11
|
23
BS[0]-BS[7]
HADR[0]-HADR[13]
PCLK1
TRCK0
149
150
104
X3501
24.576MHz
235
229
204
|
207
213
|
224
FRRV
TRRT
REC DT
REC CK
REC DT
REC CK
LBUS0-LBUS3
LBUS0-LBUS3
TRCK0
100,102
129
291-304
1-32
103-105
235,236
51-64
MC BUS MC BUS
MC BUS
105
108
TPA
NTPA
TPB
NTPB
FRRV
TRRT
VCK
CN901
CN902
CN0009
FRRV
TRRT
JL-001
BOARD(1/3) FP-090 FLEXIBLE BOARD
HDV/DV
TO
OVERALL
BLOCK DIAGRAM
(3/5)
3
VSP SO,SI,SCK
VSP2 SO,SI,SCK
VSP SO,SI,SCK
VSP2 SO,SI,SCK
5
•
6
•
4
•
3
4
•
2
•
6
•
8
VC-367 BOARD (1/5)
OSD SO
XOSD SCK
VY[0]-VY[7]
VC[0]-VC[7]
269
|
256
289
|
272
VSP SO,SI,SCK
16
(1/16)
(8/16)
(2/16)
(11/16)
IC8002
EEPROM
(11/16)
(11/16) (11/16)
(20/25)
(9/16)
(13/16)
(7/16)
(5/16)
(5/16)
(4/16)
(3/16)
(6/16)
1-3
5,6
(PAGE 3-5)
TO
OVERALL
BLOCK DIAGRAM
(4/5)
q;
(PAGE 3-8)
(PAGE 3-3)
(PAGE 3-3)
(PAGE 3-5)
VIDEO/AUDIO SIGNAL
VIDEO SIGNAL
AUDIO SIGNAL
D 2.28 V
NTSC/XPAL DET
3 7
6
X2020
X2021
55.687MHz
5
55.631MHz
1 2
NTSC/XPAL DET
NTSC/XPAL DET
VD SO,SI,SCK
(1/16)