DVP-NC625/NC665P
3-3
3-4
3-2. SYSTEM CONTROL BLOCK DIAGRAM
17
62
67
48
18
57
82
63
56
36
15
9
15
10
20
76
51
83
7
39
26
27
38
25
7
6
5
70
58
71
46
16
81
47
60
61
49
50
8
7
1 – 5 102 – 109 111 – 118 120
85 – 100
14
MB-108 BOARD (1/6)
(SEE PAGE 4-9)
IC106
IC104
SYSTEM
CONTROL
32M FLASH
IC108
1M SRAM
IC103
PLL
IC101
EEPROM
HD 0 – 15
HA 0 – 21
SIGNAL PROCESSOR
(SEE PAGE 3-7)
XARPIT
XARPCS
XWAIT
HA0
–
21
HA1
–
21
HD0
–
15
HD0
–
15
CS0X
SO0
SCO
SI0
INTERFACE
CONTROL
(SEE PAGE 3-15)
SI0
SO0
SC0
XIFCS
XIFBUSY
XFRRST
MA MUTE
XRST
INT4
XFRRST
XIFCS
MA MUTE
48/44.1k
54
53
X101
16.5MHz
XDRVMUTE
INT2
WIDE
CS5X
CKSW1
XDRVMUTE
XSDPIT
OCSW1
XLDON
XSDPCS
CKSW1
DREQ0
INTO
DACK0
CS2X
CS3X
DREQ1
DACK1
DREQ0
XAVDIT
DACK0
XAVDCS2
XAVDCS3
DREQ1
DACK1
VIDEO/AUDIO
(SEE PAGE 3-9 to 3-14)
SIGNAL PROCESSOR
(SEE PAGE 3-7)
RF/SERVO
(SEE PAGE 3-5)
05
33MARP
512FSAVD
X102
27MHz
33-1OUT
FSEL
512FS2CH
XFRRST
59
CS1X
72
XWRL
84
SRAMWE
29
SO1
SO1
30
SC1
SC1
79
XDACS
XDACS
INT1
CS4X
XWAIT
35
XRST
XRST
VIDEO/AUDIO
(SEE PAGE 3-9 to 3-14)
XRST
SCL
SDA
XRST
XRD
XWRH
512-2OUT
512-1OUT
XTI
XTO
3
27MAVD
27-1OUT
X1
X0
HD 0 – 15
HA 0 – 21
XRD
XWRH
3
CN101
5
6
8
4
1
WP
SCL
SDA
OCSW1
SCL
SDA
WP
IPSW
WIDE
AN3
XARPRST
AUDIO/VIDEO
(SEE PAGE 3-9 to 3-14)
HA 0 – 21
HD 0 – 15
IC107
OTP
or
60nsec
3.3Vp-p
IC104
tf
5
1.17msec
3.3Vp-p
IC103
3
1
42nsec
3.3Vp-p
IC103
9
q;
3
38nsec
3.3Vp-p
IC103
8
2
30nsec
3.3Vp-p
IC103
qg
4