Silicon Laboratories Si4700, Руководство по программированию

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AN332
172 Confidential Rev. 0.2
In 3-wire mode, the control registers are accessed as 16-bit entities (2 byte). In Table 22, the full 8-bit 3-wire
address is shown, including the chip’s fixed base address (A7:A4 = 1010b). The first two bytes in a command
stream uses register COMMAND1. The CMD byte occupies register COMMAND1[15:8], while ARG1 occupies
register COMMAND1[7:0]. Commands with an odd number of bytes must have the lower 8 bits of the register
containing the final argument byte filled with 0x00. Registers which are not specified by the command must either
not be written, or must be filled with 0x0000 (user's discretion). Writing register COMMAND1 causes the command
to execute. As a consequence, all registers containing applicable argument bytes must be written (in any order)
prior to writing register COMMAND1. For example, when sending the SET_PROPERTY command, write registers
COMMAND2..COMMAND3 first, then register COMMAND1. Note that ARG1 is part of register COMMAND1 and
must be written at the same time as CMD. The contents of registers STATUS/RESPONSE1..RESPONSE8 are not
valid until the CTS bit (STATUS/RESPONSE1[15]) is set. RESPONSE1[13:8] is updated after sending the
GET_INT_STATUS command. Response bytes which are not specified in the response byte stream are not
guaranteed to be 0x00 and should be ignored. For example, GET_PROPERTY has 4 bytes of response data in
registers RESPONSE1..RESPONSE2. The contents of registers RESPONSE3..RESPONSE8 are meaningless
and not guaranteed to be 0x0000. Likewise, for commands which have an odd number of response bytes, or a
single status byte, the least significant byte (bits 7:0) of the final register is meaningless, and not guaranteed to be
0x00.
Table 23 demonstrates the command and response procedure implemented in the system controller to use the 3-
wire bus mode. In this example the TX_TUNE_FREQ command is demonstrated.
Table 22. Register Map for 3-Wire Mode
3w
Addr
Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A0h COMMAND1 CMD ARG1
A1h COMMAND2 ARG2 ARG3
A2h COMMAND3 ARG4 ARG5
A3h COMMAND4 ARG6 ARG7
A4h Reserved1 Reserved Reserved
A5h Reserved2 Reserved Reserved
A6h Reserved3 Reserved Reserved
A7h Reserved4 Reserved Reserved
A8h
STATUS/
RESPONSE1
CTS ERR
RSDIN
T
RDSIN
T
ASQ-
INT
STCIN
T
RESP1
A9h RESPONSE2 RESP2 RESP3
AAh RESPONSE3 RESP4 RESP5
ABh RESPONSE4 RESP6 RESP7
ACh RESPONSE5 RESP8 RESP9
ADh RESPONSE6 RESP10 RESP11
AEh RESPONSE7 RESP12 RESP13
AFh RESPONSE8 RESP14 RESP15
Table 23. Command and Response Procedure - 3-Wire Bus Mode
Action Data Description
CMD 0x30 TX_TUNE_FREQ.
ARG1 0x00
ARG2 0x27 Set Station to 101.1 MHz
ARG3 0x7E (0x277E = 10110 with 10 kHz step size)
STATUS
→
0x80 Reply Status. Clear-to-send high.