AN332
Confidential Rev. 0.2
245
The device sets the CTS bit (and optional interrupt) to indicate that it is ready to accept the next command. The
CTS bit also indicates that the POWER_UP, GET_REV, POWER_DOWN, GET_PROPERTY, GET_INT_STATUS,
AM_TUNE_STATUS, and AM_RSQ_STATUS commands have completed execution. The CTS timing model is
shown in Figure 16 and the timing parameters for each command are shown in Table 43.
CMD
ARG1
STATUS
RESP1
RESP2
RESP3
RESP4
RESP5
0x43
0x01
→
0x80
→
0x00
→
0x01
→
0x00
→
0x2A
→
0x1A
AM_RSQ_STATUS
Clear STC interrupt.
Reply Status. Clear-to-send high.
No SNR high, low, RSSI high, or low interrupts.
Channel is valid, soft mute is not activated, and AFC is not railed
RSSI = 0x2A = 42d = 42 dBµV
SNR = 0x1A = 26d = 26 dB
CMD
STATUS
0x11
→
0x80
POWER_DOWN
Reply Status. Clear-to-send high.
Table 48. Programming Example for the AM/SW/LW Receiver (Continued)
Action
Data
Description
Содержание Si4700
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