Silicon Laboratories EMBER EM358 series, Справочное руководство, Страница: 177 / 257

EM358x
Rev. 0.4 177
Figure 10-19 show details of the output stage of a capture/compare channel.
Figure 10-19. Output Stage of Capture/Compare Channel (Channel 1)
The capture/compare block is made of a buffer register and a shadow register. Writes and reads always access
the buffer register.
In capture mode, captures are first written to the shadow register, then copied into the buffer register.
In compare mode, the content of the buffer register is copied into the shadow register which is compared to the
counter.
10.3.5 Input Capture Mode
In input capture mode, a capture/compare register (TIMx_CCRy) latches the value of the counter after a transition
is detected by the corresponding ICy signal. When a capture occurs, the corresponding INT_TIMCCyIF flag in the
INT_TIMxFLAG register is set, and an interrupt request is sent if enabled.
If a capture occurs when the INT_TIMCCyIF flag is already high, then the missed capture flag
INT_TIMMISSCCyIF in the INT_TIMxMISS register is set. INT_TIMCCyIF can be cleared by software writing a 1
to its bit or reading the captured data stored in the TIMx_CCRy register. To clear the INT_TIMMISSCCyIF bit,
write a 1 to it.
The following example shows how to capture the counter value in the TIMx_CCR1 when the TI1 input rises.
 Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the TIM_CC1S bits to 01 in the
TIMx_CCMR1 register. As soon as TIM_CC1S becomes different from 00, the channel is configured in input
and the TIMx_CCR1 register becomes read-only.
 Program the required input filter duration with respect to the signal connected to the timer, when the input is
one of the TIy (ICyF bits in the TIMx_CCMR1 register). Consider a situation in which, when toggling, the input
signal is unstable during at most 5 internal clock cycles. The filter duration must be longer than these 5 clock
cycles. The transition on TI1 can be validated when 8 consecutive samples with the new level have been
detected (sampled at PCLK frequency). To do this, write the TIM_IC1F bits to 0011 in the TIMx_CCMR1
register.

Select the edge of the active transition on the TI1 channel: Write the TIM_CC1P bit to 0 in the TIMx_CCER
register (rising edge in this case).

Program the input prescaler: In this example, the capture is to be performed at each valid transition, so the
prescaler is disabled (write the TIM_IC1PSC bits to 00 in the TIMx_CCMR1 register).

Enable capture from the counter into the capture register: Set the TIM_CC1E bit in the TIMx_CCER register.

If needed, enable the related interrupt request by setting the INT_TIMCC1IF bit in the INT_TIMxCFG register.

When an input capture occurs:
 The TIMx_CCR1 register gets the value of the counter on the active transition.
 INT_TIMCC1IF flag is set (capture/compare interrupt flag). The missed capture/compare flag
INT_TIMMISSCC1IF in INT_TIMxMISS is also set if another capture occurs before the INT_TIMCC1IF
flag is cleared.
 An interrupt may be generated if enabled by the INT_TIMCC1IF bit.