SICK UE4740, Руководство по эксплуатации

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Operating Instructions Chapter 11
UE4740
8020182/1CUO/2022-08-26 © SICK AG • Industrial Safety Systems • Germany • All rights reserved
43
Subject to change without notice
Annex
11.6 List of tables
Tab. 1: Overview of disposal by component .................................................................... 10
Tab. 2: Meaning of the status indicators ........................................................................ 13
Tab. 3: Terminal assignment of the UE4740 EFI gateway .............................................. 19
Tab. 4: Terminal assignment of the FX3-MPL1 system plug ........................................... 19
Tab. 5: Pin assignment Ethernet connection UE4740 (RJ-45 plug) ................................ 20
Tab. 6: Pin assignment configuration connection (M8

×

4) ............................................. 20
Tab. 7: Connection possibilities for the Configuration & Diagnostic Software (CDS) ...... 25
Tab. 8: Error displays of the LEDs at the EFI gateway ..................................................... 29
Tab. 9: Special aspects of the LED error displays of the PROFIsafe ............................... 30
Tab. 10: Special LED error displays for PROFINET IO ........................................................ 30
Tab. 11: EFI gateway data sheet ....................................................................................... 32
Tab. 12:
Data for calculating the “maximum reaction time” of the entire system ............ 34
Tab. 13: Determining the response time from the EFI interface to the PROFINET IO
connection .......................................................................................................... 34
Tab. 14: Part numbers EFI gateway .................................................................................. 36
Tab. 15: Accessories part numbers .................................................................................. 36
Tab. 16: Structure of the UE4740 process images ........................................................... 37
Tab. 17: Process image of the input signals from the EFI connection to the (F)PLC ......... 38
Tab. 18: Process image of the output signals from the FPLC to the EFI connection......... 39
Tab. 19: Diagnostics data of the UE4740 ......................................................................... 39
Tab. 20: Additional diagnostics of the UE4740 ................................................................ 40
Tab. 21: Values for ChannelErrorType on the UE4740 ..................................................... 40
11.7 List of illustrations
Fig. 1: Operating principle of the UE4740 EFI gateway ................................................. 11
Fig. 2: Status indicators of the UE4740 EFI gateway..................................................... 12
Fig. 3: Mounting of the EFI gateway ............................................................................... 16
Fig. 4: Terminal assignment of the UE4740 EFI gateway .............................................. 19
Fig. 5: Pin assignment configuration connection (M8

×

4) ............................................. 20
Fig. 6: Dimensional drawing UE4740 EFI gateway (mm) ............................................... 35