[2] Circuit description of control PWB
1. General description
Fig. 2 shows the functional blocks of the control PWB, which is com-
posed of 5 blocks.
Fig. 2 Control PWB functional block diagram
2. Description of each block
(1) Main control block
The main control block is composed of ROCKWELL 1 chip fax engine
(XFC-MVP), ROM (256KByte), RAM (32KByte), DRAM (256KByte),
FLASH MEMORY (512KByte). Devices are connected to the bus to
control the whole unit.
1) XFC-MVP (IC3) : pin-144 QFP (XFC-MVP)
The FAXENGINE Integrated Facsimile Controllers.
XFC-MVP, contains an internal 8 bit microprocessor with an external
16 Mbyte address space and dedicated circuitry optimized for facsim-
ile image processing and facsimile machine control and monitoring.
2) 27C040 (IC2): pin-32 DIP (ROM)
EPROM of 4Mbit equipped with software for the main CPU.
3) SRM2B257SL70 (IC6): pin-28 SOP (RAM)
Line memory for the main CPU system RAM area and coding/decod-
ing process. Used as the transmission buffer.
Memory of recorded data such as daily report and auto dials. When
the power is turned off, this memory is backed up by the lithium
battery.
4) MB81C4256A (IC7, 15): pin-26 SOJ (RAM)
Image memory for recording process.
•
Memory for recording pixel data at without paper.
5) LH28F004SU (IC8): pin-40 TSOP (FLASH)
This is a 4Mbit flash memory to store the voice data/image.
PANEL
CONTROL
BLOCK
IMAGE
SIGNAL
PROCESS
BLOCK
MAIN
CONTROL
BLOCK
MODEM/
CONTROL
BLOCK
MECHANISM/
RECORDING
CONTROL
BLOCK
MC24 CPU Control IF
MC24 Megacell (8bit Data,24bit Address)
WatchdogTimer
Real Time Clock
Crystal Oscillator
Battery Back-up Circuit
Interrupt Controller
BUS Interface
DRAM Control
Internal & External Bus Control
Internal & External Decode
DMA controller
CPU Bus
1K Intermal RAM
MC24 CPU
Shading correction
Line butter
General I/O
Motor Control
GPIO
Tone
Video Port
SART
Autobaud
Scanner Control & Video
Processing
6-Bit FADC
CCD/CIS Scanner
5ms,A4/B4 Lines
Shading Correction (1:1,1:8)
Edge Enhancement & Dithering
Multilevel B4-A4 Reduction
Dynamic ABC & Contrast Control
BI-level Resolution
Convention
Programmable
Reduction &
Expansion
T.4/T.6 CODEC
MH, MR, MMR
Haroware
Altemate
Compression &
Decompression
Thermal Printer IF
5 ms Line Time
A4/B4 Lines
TPH ADC
4 Strobe TPH
Latchless TPH
External DMA I/F
Operator Panel IF
32 keys
8 LEDs
LCD Module
SYSCLK
TSTCLK
DEBUGN
RESETN
XIN
XOUT
VBAT
VDRAM
PWRDWNN
BATRSTN
BATRSTN
OPO [7:0]
OPI [3:0]
LEDCTL
LCDCS
PCLK/DMAACK
PDAT
PLAT
STRB [3:0]
THADIN
STRBPOL/DMAREQ
Internal CPU Bus
DMA Bus
External CPU Bus
MIRQN
A [23:0]
D [7:0]
RDN
WRN
ROMCSN
CSN [1:0]
MCSN
SYNC
REGDMA
WAITN
RASN
CASN[2:0]
DWRN
TONE
GPIO [7:0]/V ID [7:0]
GPIO [10:8]/VDC [2:0]
GPO11/BE/SERIN
GPIO12/CS2N/SCLK
GPIO13/CS3N/TXD
GPIO14/CS4N/RXD
GPIO15/CS5N
GPIO16/IRQ8
GPIO17/IRQ5N
GPIO18/IRQ10N
GP19/RDY/SERO
PM [3:0]/GPO [3:0]
SM [3:0]/GPO [3:0]
–VREF
+VREF
VIN
START
CLK1
CLK1N
CLK2
VIDCTL[1:0]
PWR/GND
TEST
Fig. 3
FO-1850TH
5 – 2
Содержание FO-1850
Страница 65: ...M E M O FO 1850TH 5 13 ...
Страница 73: ...Control PWB parts layout Top side 6 8 FO 1850TH ...
Страница 74: ...Control PWB parts layout Bottom side 6 9 FO 1850TH ...
Страница 76: ...TEL LIU PWB parts layout 6 11 FO 1850TH ...
Страница 78: ...6 13 Power supply PWB parts layout FO 1850TH ...
Страница 81: ...Operation panel PWB parts layout 6 16 FO 1850TH ...
Страница 83: ...Joint PWB parts layout 6 18 FO 1850TH ...
Страница 96: ...M E M O FO 1850TH 8 9 ...