aPPenDiX B POWeR SaVinG
S1C17153 TeChniCal Manual
Seiko epson Corporation
aP-B-1
(Rev. 1.0)
Appendix B Power Saving
Current consumption will vary dramatically, depending on CPU operating mode, operation clock frequency, and the
peripheral circuits being operated. Listed below are the control methods for saving power.
Clock Control Power Saving
B.1
This section describes clock systems that can be controlled via software and power-saving control details. For more
information on control registers and control methods, refer to the respective module sections.
System SleeP
• Execute the
slp
instruction (when RTC is stopped)
When the entire system can be stopped, stop the RTC and execute the
slp
instruction. The CPU enters
SLEEP mode and the OSC1A/OSC3B clocks stop. This also stops all peripheral circuits using the OSC1A/
OSC3B clocks. Starting up the CPU from SLEEP mode is therefore limited to startup using a port (described
later).
• Execute the
slp
instruction (when RTC is running)
When the system except the RTC for time keeping can be stopped, maintain the RTC in running state and
execute the
slp
instruction. The CPU enters SLEEP mode and the OSC3B clock stops. This also stops all
peripheral circuits using the OSC3B clock. Starting up the CPU from SLEEP mode is therefore limited to
startup using a port or RTC (described later).
System clocks
• Select a low-speed clock source (CLG module)
Select a low-speed oscillator for the system clock source. You can reduce current consumption by selecting
the OSC1A clock when low-speed processing is possible.
• Disable unnecessary oscillator circuits (CLG module)
Operate the oscillator comprising the system clock source. Where possible, stop the other oscillators. You can
reduce current consumption by using OSC1A as the system clock and disable the OSC3B oscillator.
CPu clock (CClK)
• Execute the
halt
instruction
Execute the
halt
instruction when program execution by the CPU is not required, for example, when the
system is waiting for an interrupt. The CPU enters HALT mode and suspends operations, but the peripheral
circuits maintain the status in place at the time of the
halt
instruction, enabling use of peripheral circuits for
generating interrupts and the LCD driver. You can reduce power consumption even further by suspending un-
necessary oscillator and peripheral circuits before executing the
halt
instruction. The CPU is started from
HALT mode by an interrupt from a port or the peripheral circuit operating in HALT mode.
• Select a low-speed clock gear (CLG module)
The CLG module can reduce CPU clock speeds to between 1/1 and 1/8 of the system clock via the clock gear
settings. You can reduce current consumption by operating the CPU at the minimum speed required for the
application.
Peripheral clock (PClK)
• Stop PCLK (CLG module)
Stop the PCLK clock supplied from the CLG to peripheral circuits if none of the following peripheral circuits
is required.
Peripheral circuits that use PCLK
• Interrupt controller
• 8-bit timer Ch.0
• SPI Ch.0
• Power generator
• P ports and port MUX (control registers, chattering filters)
• MISC registers
