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13 WaTChDOG TiMeR (WDT)

S1C17153 TeChniCal Manual

Seiko epson Corporation

13-1

(Rev. 1.0)

Watchdog Timer (WDT)

13

WDT Module Overview

13.1

The S1C17153 includes a watchdog timer module (WDT) that uses the OSC1A oscillator as its clock source. This
timer is used to detect CPU runaway.
The features of WDT are listed below.
• 10-bit up counter
• Either reset or NMI can be generated if the counter overflows.
Figure 13.1.1 shows the WDT configuration.

NMI

Reset

10-bit counter

Interrupt

control circuit

Run/Stop control

NMI/reset mode select

WDTRUN[3:0]

WDTMD

Watchdog timer reset

WDTRST

Watchdog timer

RTC reset

SLEEP/NORMAL

32 kHz

256 Hz

OSC1A
oscillator

OSC1A
divider

CLG

1.1 WDT Configuration

Figure 13.

The WDT module generates an NMI or reset (selectable via software) to the CPU if not reset within 131,072/f

OSC1A

seconds (4 seconds when f

OSC1A

= 32.768 kHz).

Reset WDT via software within this cycle to prevent NMI/resets, which in turn enables runaway detection for pro-
grams that do not pass through the handler routine.

Operation Clock

13.2

The WDT module uses the 256 Hz clock output by the CLG module (256 Hz clock derived from the OSC1A di-
vider) as the operation clock. Therefore, the OSC1A oscillator must be turned on before starting the WDT module.
However, the clock is not supplied to the WDT module in SLEEP mode even if the OSC1A oscillator is on. For
detailed information on clock control, see the “Clock Generator (CLG)” chapter.

notes

: • The WDT module input clock frequency is 256 Hz only when the OSC1A clock frequency is

32.768 kHz. The frequency and time described in this chapter will vary accordingly for other
OSC1A clock frequencies.

• The OSC1A divider is reset when the RTC starts running (when 1 is written to RTCRUN/RTC_

CTL register). This affects the count operations of the WDT module, as new 256 Hz clock
cycle begins from that point.

WDT Control

13.3

nMi/Reset Mode Selection

13.3.1

WDTMD/WDT_ST register is used to select whether an NMI signal or a reset signal is output when WDT has not
been reset within the NMI/reset generation cycle.
To generate an NMI, set WDTMD to 0 (default). Set to 1 to generate a reset.

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Содержание S1C17153

Страница 1: ...Rev 1 0 CMOS 16 BiT SinGle ChiP MiCROCOnTROlleR S1C17153 Technical Manual...

Страница 2: ...any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or c...

Страница 3: ...number Model name C microcomputer digital products Product classification S1 semiconductor Development tools S5U1 C 17000 H2 1 Packing specifications 00 standard packing Version 1 Version 1 Tool type...

Страница 4: ...rea 3 3 3 3 1 Embedded RAM 3 3 3 4 Display RAM area 3 3 3 5 Internal Peripheral Area 3 3 3 5 1 Internal Peripheral Area 1 0x4000 3 3 3 5 2 Internal Peripheral Area 2 0x5000 3 3 3 6 S1C17 Core I O Area...

Страница 5: ...TB 7 7 7 8 Control Register Details 7 8 Clock Source Select Register CLG_SRC 7 8 Oscillation Control Register CLG_CTL 7 9 FOUTA Control Register CLG_FOUTA 7 10 FOUTB Control Register CLG_FOUTB 7 11 Os...

Страница 6: ...10 7 T8 Output Signals 10 4 10 8 T8 Interrupts 10 4 10 9 Control Register Details 10 5 T8 Ch x Count Clock Select Register T8_CLKx 10 5 T8 Ch x Reload Data Register T8_TRx 10 5 T8 Ch x Counter Data Re...

Страница 7: ...Modes 13 2 13 4 Control Register Details 13 2 Watchdog Timer Control Register WDT_CTL 13 2 Watchdog Timer Status Register WDT_ST 13 3 14 uaRT 14 1 14 1 UART Module Overview 14 1 14 2 UART Input Output...

Страница 8: ...lator Control Register LCD_VREG 16 12 LCD Interrupt Mask Register LCD_IMSK 16 12 LCD Interrupt Flag Register LCD_IFLG 16 12 17 Sound Generator SnD 17 1 17 1 SND Module Overview 17 1 17 2 SND Output Pi...

Страница 9: ...0x4107 0x506c UART with IrDA Ch 0 AP A 3 0x4240 0x4248 8 bit Timer Ch 0 AP A 4 0x4306 0x4314 Interrupt Controller AP A 4 0x4320 0x4326 SPI Ch 0 AP A 4 0x5000 0x5003 Clock Timer AP A 5 0x5040 0x5041 Wa...

Страница 10: ...ol Peripheral module clock supply control lCD driver Number of driver outputs Segment output 32 pins Common output 4 pins Other Includes a power supply voltage booster reducer Includes a display data...

Страница 11: ...g form Aluminum pad chip Block Diagram 1 2 CPU Core S1C17 Internal RAM 2K bytes 8 bit timer 1 ch Clock generator with oscillators Clock timer Watchdog timer 16 bit PWM timer 1 ch MISC register Power g...

Страница 12: ...CB CA VSS VDD VD1 OSC1 OSC2 TEST RESET P00 SIN0 P01 SOUT0 P02 SCLK0 FOUTA SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 Y X 0 0...

Страница 13: ...0 896 5 44 COM1 256 0 896 5 12 SEG29 469 0 896 5 45 COM0 336 0 896 5 13 SEG28 549 0 896 5 46 VC3 811 0 840 5 14 SEG27 811 0 858 3 47 VC2 811 0 760 5 15 SEG26 811 0 778 3 48 VC1 811 0 680 5 16 SEG25 81...

Страница 14: ...O I Pull up I O port pin with port input interrupt function SOUT0 O UART Ch 0 data output pin 60 P02 I O I Pull up I O port pin with port input interrupt function SCLK0 I UART Ch 0 external clock inpu...

Страница 15: ...structions 111 basic instructions 184 including variations Execution cycle Main instructions executed in one cycle Extended immediate instructions Immediate extended up to 24 bits Compact and fast ins...

Страница 16: ...y address post increment post decrement and pre decrement functions can be used rb rs rb rs rb rs sp imm7 rs General purpose register byte stack imm7 rs General purpose register byte memory ld ub rd r...

Страница 17: ...of general purpose register and immediate sp imm7 24 bit addition of SP and immediate adc rd rs 16 bit addition with carry between general purpose registers Supports conditional execution c executed...

Страница 18: ...xt imm13 Extend operand in the following instruction Conversion cv ab rd rs Converts signed 8 bit data into 24 bits cv as rd rs Converts signed 16 bit data into 24 bits cv al rd rs Converts 32 bit dat...

Страница 19: ...er with address pre decremented sp Stack pointer sp sp imm7 Stack sp Stack with address post incremented sp Stack with address post decremented sp Stack with address pre decremented imm3 imm5 imm7 imm...

Страница 20: ...0 default D0 PSRN PSR Negative N Flag Bit The value of the PSR N negative flag can be read out 1 R 1 0 R 0 default Processor information 2 5 The S1C17153 has the IDIR register shown below that allows...

Страница 21: ...x5200 0x523f 0x51a0 0x51ff 0x5180 0x519f 0x5140 0x517f 0x5120 0x513f 0x5100 0x511f 0x50c0 0x50ff 0x50a0 0x50bf 0x5060 0x509f 0x5040 0x505f 0x5020 0x503f 0x5000 0x501f reserved Real time clock reserved...

Страница 22: ...ea and accesses data in the internal ROM area When the S1C17153 executes the instruction stored in the internal RAM area and accesses data in the internal RAM area internal ROM area 3 2 embedded ROM 3...

Страница 23: ...ddress 0x5000 For details of each control register see the I O register list in Appendix or description for each peripheral module internal Peripheral area 1 0x4000 3 5 1 The internal peripheral area...

Страница 24: ...ers listed in the table below are located 6 1 I O Map S1C17 Core I O Area Table 3 Peripheral address Register name Function S1C17 Core I O 0xffff84 IDIR Processor ID Register Indicates the processor I...

Страница 25: ...r supply circuit VC regulator voltage booster halver VC1 VC3 LHVLD 2 1 Configuration of Internal Power Supply Circuit Figure 4 The internal power supply circuit consists of a VD1 regulator and an LCD...

Страница 26: ...nd OSC1A using LCDBCLKSRC 1 0 LCD_BCLK register 2 2 2 Clock Source Selection Table 4 lCDBClKSRC 1 0 Clock source 0x3 0x2 Reserved 0x1 OSC1A 0x0 OSC3B Default 0x0 Booster clock division ratio selection...

Страница 27: ...l Register Controls the VD1 regulator The power control registers are described in detail below Note When data is written to the registers the Reserved bits must always be written as 0 and not 1 LCD B...

Страница 28: ...d D0 VCSEL Reference voltage select 1 VC2 0 VC1 0 R W D 7 5 Reserved D4 LHVLD VC Heavy Load Protection Mode Bit Sets the VC regulator into heavy load protection mode 1 R W Heavy load protection On 0 R...

Страница 29: ...being read D 7 6 Reserved D5 HVLD VD1 Heavy Load Protection Mode Bit Sets the VD1 regulator into heavy load protection mode 1 R W Heavy load protection On 0 R W Heavy load protection Off default The...

Страница 30: ...ESET pin must be held at low for more than the prescribed time see Input Output Pin Characteris tics in the Electrical Characteristics chapter after the power supply voltage is supplied When the RESET...

Страница 31: ...d may be longer than that indicated in the figure below Boot vector OSC3B oscillation stabilization waiting time Internal reset hold period Booting OSC3B clock RESET Internal reset Internal data reque...

Страница 32: ...rity for determining the processing sequence when multiple interrupts oc cur simultaneously to be set for each interrupt system separately Each interrupt system includes the number of interrupt causes...

Страница 33: ...pt Frame signal 11 0x0b TTBR 0x2c 16 bit PWM timer Ch 0 interrupt Compare A B Capture A B Capture A B overwrite 12 0x0c TTBR 0x30 reserved 13 0x0d TTBR 0x34 14 0x0e TTBR 0x38 8 bit timer Ch 0 interrup...

Страница 34: ...Note To prevent recurrence of the interrupt due to the same cause of interrupt always reset the inter rupt flag in the peripheral module before enabling the interrupt resetting the PSR or executing th...

Страница 35: ...d until the above conditions are subsequently met The S1C17 Core samples interrupt requests for each cycle On accepting an interrupt request the S1C17 Core switches to interrupt processing immediately...

Страница 36: ...the LCD and T16A2 Ch 0 interrupt levels 0x4310 ITC_LV5 Interrupt Level Setup Register 5 Sets the T8 Ch 0 interrupt level 0x4312 ITC_LV6 Interrupt Level Setup Register 6 Sets the UART Ch 0 interrupt l...

Страница 37: ...2 Interrupt Level Bits Table 6 Register Bit interrupt ITC_LV0 0x4306 ILV0 2 0 D 2 0 P0 port interrupt ILV1 2 0 D 10 8 Reserved ITC_LV1 0x4308 ILV2 2 0 D 2 0 Reserved ILV3 2 0 D 10 8 Clock timer inter...

Страница 38: ...8 Controls the clock supply to the peripheral modules Turns the clocks on and off according to the CPU operating status RUN HALT or SLEEP Supports quick restart processing from SLEEP mode Turns OSC3B...

Страница 39: ...nerates a sub clock for timers and low power operations The OSC3B clock is selected as the system clock after an initial reset Oscillator on off switching and system clock selection from OSC3B and OSC...

Страница 40: ...an initial reset This means the CPU can start operating when the CPU operation start time at initial reset indicated below at a maximum has elapsed after the reset state is can celed For the oscillati...

Страница 41: ...SC1A stops in SLEEP mode regardless of how OSC1EN is set After an initial reset OSC1EN and RTCRUN are both set to 0 and the OSC1A oscillator circuit is halted 3 2 1 OSC1A Oscillator Operating Status n...

Страница 42: ...itching The oscillator circuit that is not selected as the system clock source and is not used for running peripheral circuits can be shut down to reduce current consumption 4 1 System Clock Selection...

Страница 43: ...clock speeds 5 1 CCLK Gear Ratio Selection Table 7 CClKGR 1 0 Gear ratio 0x3 1 8 0x2 1 4 0x1 1 2 0x0 1 1 Default 0x0 Clock supply control The CCLK clock supply is stopped by executing the halt instru...

Страница 44: ...t used as the clock source can not be disabled see Section 7 7 or each peripheral module chapter The PCLK supply can be disabled Sound generator 16 bit PWM timer UART FOUTA FOUTB outputs Clock externa...

Страница 45: ...n wait time and other conditions Control Register Details 7 8 8 1 List of CLG Registers Table 7 address Register name Function 0x5060 CLG_SRC Clock Source Select Register Selects the clock source 0x50...

Страница 46: ...as the system clock source cannot be turned off Continuous write read access to CLKSRC 1 0 is prohibited At least one instruction unre lated to CLKSRC 1 0 access must be inserted between the write and...

Страница 47: ...ed OSC1A OSC3B D1 reserved 0 when being read D0 FOUTAE FOUTA output enable 1 Enable 0 Disable 0 R W D7 Reserved D 6 4 FOUTAD 2 0 FOUTA Clock Division Ratio Select Bits Selects the source clock divisio...

Страница 48: ...0x7 1 128 0x6 1 64 0x5 1 32 0x4 1 16 0x3 1 8 0x2 1 4 0x1 1 2 0x0 1 1 Default 0x0 D 3 2 FOUTBSRC 1 0 FOUTB Clock Source Select Bits Selects the FOUTB clock source 8 7 FOUTB Clock Source Selection Table...

Страница 49: ...k system supply wait time OSC3B oscillation start time max OSC3B os cillation stabilization wait time D 5 2 Reserved D 1 0 OSC1AWT 1 0 OSC1A Stabilization Wait Cycle Select Bits An oscillation stabili...

Страница 50: ...the peripheral modules listed above are not required Peripheral modules functions that do not use PCLK Real time clock Clock timer Watchdog timer LCD driver Sound generator SVD circuit 16 bit PWM tim...

Страница 51: ...7 ClOCK GeneRaTOR ClG 7 14 Seiko Epson Corporation S1C17153 Technical Manual Rev 1 0 8 11 CCLK Gear Ratio Selection Table 7 CClKGR 1 0 Gear ratio 0x3 1 8 0x2 1 4 0x1 1 2 0x0 1 1 Default 0x0...

Страница 52: ...er 10 m 1 h Half day 1 day 32 kHz 256 Hz OSC1A oscillator OSC1A divider CLG 1 Hz 32 Hz 8 Hz 4 Hz 1 Hz Internal data bus Divider AM PM RTC Reset RTCRUN 1 1 RTC Block Diagram Figure 8 RTC Counters 8 2 T...

Страница 53: ...git RTCHOUR 5 4 0 2 10 hour digit RTCHOUR 5 0 12 hour mode 1 12 RTCHOUR 3 0 0 9 1 hour digit RTCHOUR 5 4 0 1 10 hour digit 2 3 Hour Counter Figure 8 2 1 Hour Counter Values Table 8 Time 24 hour mode 1...

Страница 54: ...SC1A oscillation stabilization time Time until RTC is restarted 12 hour 24 hour mode selection 8 3 2 Whether to use the clock in 12 hour or 24 hour mode can be selected using RTC24H RTC_CTL register R...

Страница 55: ...ely after starting the RTC Counter Read 8 3 5 If 1 is being carried over while the counters are being read correct time may not be read Counter values should be read in the procedure shown below Read...

Страница 56: ...ITC Since the RTC is active even in SLEEP mode RTC interrupt requests may be used to cancel SLEEP mode For more information on interrupt processing see the Interrupt Controller ITC chapter Notes To p...

Страница 57: ...0 R W Stop default The RTCRUN default setting is 0 which stops the RTC Setting RTCRUN to 1 enables the CLG to send the clock to the RTC When RTCRUN is set to 1 the OSC1A oscillator circuit does not st...

Страница 58: ...Register RTC_IFLG 0x56c4 16 bits D15 10 reserved 0 when being read D9 INT1D 1 day interrupt flag 1 Cause of interrupt occurred 0 Cause of interrupt not occurred 0 R W Reset by writing 1 D8 INTHD Half...

Страница 59: ...2 Hz Interrupt Flag Bit Indicates 32 Hz interrupt cause occurrence status INT32HZ is set to 1 in the divider 32 Hz signal cycles RTC Minute Second Counter Register RTC_MS Register name address Bit nam...

Страница 60: ...be fixed at 0 immediately after RTC24H RTC_CTL register is changed from 12 hour mode to 24 hour mode D6 Reserved D 5 0 RTCHOUR 5 0 Hour Counter Bits These bits are used to read and write data from to...

Страница 61: ...can generate input interrupts at the signal edge selected with software The P0 ports include a chattering filter Can generate an initial reset by entering low level simultaneously to the P0 ports sele...

Страница 62: ...the I O ports see the descriptions of the peripheral modules indicated in parentheses The sections below describe port functions with the pins set as general purpose I O ports Data input Output 9 3 D...

Страница 63: ...disabled individually for each bit using PxPUy Px_ PU register Setting PxPUy to 1 default enables the pull up resistor and pulls up the port pin in input mode It will not be pulled up if set to 0 The...

Страница 64: ...eset in the interrupt handler routine after a port interrupt has occurred to prevent recurring interrupts To prevent generating unnecessary interrupts reset the relevant P0IFy before enabling inter ru...

Страница 65: ...edge for generating P0 port interrupts 0x5207 P0_IFLG P0 Port Interrupt Flag Register Indicates resets the P0 port interrupt occurrence status 0x5208 P0_CHAT P0 Port Chattering Filter Control Register...

Страница 66: ...s Px_OEN Register name address Bit name Function Setting init R W Remarks Px Port Output Enable Register Px_OEN 0x5202 0x5212 8 bits D7 0 PxOEN 7 0 Px 7 0 port output enable 1 Enable 0 Disable 0 R W N...

Страница 67: ...Select Register P0_EDGE Register name address Bit name Function Setting init R W Remarks P0 Port Interrupt Edge Select Register P0_EDGE 0x5206 8 bits D7 0 P0EDGE 7 0 P0 7 0 port interrupt edge select...

Страница 68: ...fPCLK 256 fPCLK None Note This register is available for the P0 ports D7 Reserved D 6 4 P0CF2 2 0 P0 7 4 Chattering Filter Time Select Bits Configures the chattering filter circuit for the P0 7 4 por...

Страница 69: ...y inputting Low level simultaneously to the ports selected here For example if P0KRST 1 0 is set to 0x3 an initial reset is performed when the four ports P00 to P03 are simultaneously set to Low level...

Страница 70: ...ed reserved SOUT0 P01 D1 0 P00MUX 1 0 P00 port function select P00MUX 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved reserved SIN0 P00 The P00 to P03 port pins are shared with the peripheral module pin...

Страница 71: ...P04MUX 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved reserved TOUTA0 CAPA0 P04 The P04 to P07 port pins are shared with the peripheral module pins This register is used to select how the pins are use...

Страница 72: ...0x0 reserved BZ P11 reserved D1 0 P10MUX 1 0 P10 port function select P10MUX 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved SPICLK0 FOUTB P10 The P10 to P13 port pins are shared with the peripheral mod...

Страница 73: ...erflow Run stop control Internal data bus Count clock select Interrupt request Clock outputs To ITC To SPI PCLK PRESER Timer reset Down counter T8_TCx Control circuit Count mode select TRMD 8 bit time...

Страница 74: ...ts the reload data register value into the counter and continues the count Thus the timer periodically outputs an underflow pulse T8 should be set to this mode to generate periodic in terrupts at desi...

Страница 75: ...ction 10 3 3 Calculate the initial counter value and set it to the reload data register See Section 10 4 4 Reset the timer to preset the counter to the initial value See Section 10 5 5 When using time...

Страница 76: ...nt clock frequency Hz TR Reload data 0 255 bps Transfer rate bits s T8 interrupts 10 8 The T8 module outputs an interrupt request to the interrupt controller ITC when the counter underflows underflow...

Страница 77: ...lock PCLK 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reserved 1 16384 1 8192 1 4096 1 2048 1 1024 1 512 1 256 1 128 1 64 1 32 1 16 1 8 1 4 1 2 1 1 D 15 4 Reserved D 3 0 DF 3 0 Cou...

Страница 78: ...15 5 Reserved Do not write 1 D4 TRMD Count Mode Select Bit Selects the count mode 1 R W One shot mode 0 R W Repeat mode default Setting TRMD to 0 sets the timer to repeat mode In this mode once the c...

Страница 79: ...not occurred 0 R W Reset by writing 1 D 15 9 Reserved D8 T8IE T8 Interrupt Enable Bit Enables or disables interrupts caused by counter underflows 1 R W Interrupt enabled 0 R W Interrupt disabled defa...

Страница 80: ...er Comparator circuit TOUT control circuit Interrupt control circuit TOUTA0 TOUTB0 CAPA0 CAPB0 Interrupt request Compare B Capture B register T16A_CCB0 Compare A Capture A register T16A_CCA0 Counter b...

Страница 81: ...ers to a channel number 0 Example T16A_CTLx register TOUTAx pin Ch 0 T16A_CTL0 register TOUTA0 T16a2 input Output Pins 11 2 Table 11 2 1 lists the input output pins for the T16A2 module 2 1 List of T1...

Страница 82: ...internal clock OSC3B or OSC1A is selected use T16ACLKD 3 0 T16A_CLKx register to select the division ratio 3 3 Internal Clock Division Ratio Selection Table 11 T16aClKD 3 0 Division ratio Clock source...

Страница 83: ...second CCA Compare A register value set 0 to 65535 CCB Compare B register value set 0 to 65535 ct_clk Count clock frequency Hz The compare A and compare B signals are also used to generate a timer ou...

Страница 84: ...clock cycle time The setting of CAPATRG 1 0 or CAPBTRG 1 0 is ineffective in comparator mode No counter capturing op eration will be performed even if a trigger edge is specified The capture mode cann...

Страница 85: ...ounter Run STOP Control 11 5 2 Make the following settings before starting the count operation 1 Switch the input output pin functions to be used for T16A2 Refer to the I O Ports P chapter 2 Select op...

Страница 86: ...11 5 4 2 Operation Timing in Capture Mode Figure 11 Timer Output Control 11 6 The timer that has been set in comparator mode can generate TOUT signals using the compare A and compare B signals and ca...

Страница 87: ...le 0x2 Toggle No change 0x1 Rise Fall 0x0 Disable output Default 0x0 TOUTAMD 1 0 and TOUTBMD 1 0 are also used to turn the TOUT outputs On and Off TOuT signal polarity selection By default an active H...

Страница 88: ...1 2n 0 1 1 2 n 1 n 0 1 1 2 3 4 2n 4 2n 3 2n 2 2n 1 n T16A_CCBx Count clock T16A_TCx Dual edge counter TOUTAx TOUTBx Example HCM 1 T16A_CCAx 1 and T16A_CCBx 5 When TOUTAMD 1 0 TOUTBMD 1 0 0x1 and TOUTA...

Страница 89: ...s for this cause is not sent to the ITC Capture a overwrite interrupt This interrupt request is generated if the capture A register is overwritten by a new external trigger when the capture A interrup...

Страница 90: ...a T16A_IEN0 T16A Compare Capture Ch 0 Interrupt Enable Register Enables disables interrupts 0x540c T16A_IFLG0 T16A Compare Capture Ch 0 Interrupt Flag Register Displays sets interrupt occurrence statu...

Страница 91: ...ds the clock selected as above to the counter If timer operation is not required disable the clock supply to reduce current consumption T16A Counter Ch x Control Register T16A_CTLx Register name addre...

Страница 92: ...values with the compare A and B buffer values instead of the compare A and B register values The compare A and B register values written via software are loaded to the compare A and B buffers when the...

Страница 93: ...reserved 0 when being read D9 TOUTBINV TOUT B invert 1 Invert 0 Normal 0 R W D8 CCBMD T16A_CCB register mode select 1 Capture 0 Comparator 0 R W D7 6 CAPATRG 1 0 Capture A trigger select CAPATRG 1 0...

Страница 94: ...Capture A Trigger Select Bits Selects the trigger edge s of the external signal CAPAx at which the counter value is captured in the capture A register 8 6 Capture A Trigger Edge Selection Table 11 Ca...

Страница 95: ...gnal is asserted and a cause of compare A interrupt occurs Furthermore the TOUT output waveform changes when TOUTAMD 1 0 T16A_CCCTLx register or TOUTBMD 1 0 T16A_ CCCTLx register is set to 0x2 or 0x1...

Страница 96: ...0 R W Interrupt disabled default Setting CAPBOWIE to 1 enables capture B overwrite interrupt requests to the ITC Setting it to 0 dis ables interrupts D4 CAPAOWIE Capture A Overwrite Interrupt Enable...

Страница 97: ...rwrite Interrupt Flag Bit Indicates whether the cause of capture A overwrite interrupt has occurred or not 1 R Cause of interrupt has occurred 0 R No cause of interrupt has occurred default 1 W Flag i...

Страница 98: ...egister CBIF is reset by writing 1 D0 CAIF Compare A Interrupt Flag Bit Indicates whether the cause of compare A interrupt has occurred or not 1 R Cause of interrupt has occurred 0 R No cause of inter...

Страница 99: ...data for each bit 128 Hz to 1 Hz to be read out by software The clock timer can also generate interrupts using the 32 Hz 8 Hz 2 Hz and 1 Hz signals This clock timer is normally used for various timin...

Страница 100: ...32 Hz interrupt 8 Hz interrupt 2 Hz interrupt 1 Hz interrupt OSC1A 128 CTCNT0 CTCNT1 CTCNT2 CTCNT3 CTCNT4 CTCNT5 CTCNT6 CTCNT7 4 1 Clock Timer Timing Chart Figure 12 Notes The clock timer switches to...

Страница 101: ...rrupt The interrupt flag is reset by writing 1 Control Register Details 12 6 6 1 List of CT Registers Table 12 address Register name Function 0x5000 CT_CTL Clock Timer Control Register Resets and star...

Страница 102: ...32 Hz 8 Hz 2 Hz and 1 Hz signals Setting CTIE to 1 enables CT interrupts for the corresponding frequency signal falling edge while setting to 0 disables interrupts D 7 4 Reserved D3 CTIE32 32 Hz Inter...

Страница 103: ...f 8 Hz interrupt has occurred or not 1 R Cause of interrupt has occurred 0 R No cause of interrupt has occurred default 1 W Flag is reset 0 W Ignored D1 CTIF2 2 Hz Interrupt Flag Bit Indicates whether...

Страница 104: ...o grams that do not pass through the handler routine Operation Clock 13 2 The WDT module uses the 256 Hz clock output by the CLG module 256 Hz clock derived from the OSC1A di vider as the operation cl...

Страница 105: ...f the NMI The WDTST set to 1 is cleared to 0 by reset ting WDT Operations in halT and SleeP Modes 13 3 4 halT mode The WDT module operates in HALT mode as the clock is supplied HALT mode is therefore...

Страница 106: ...er WDT_ST Register name address Bit name Function Setting init R W Remarks Watchdog Timer Status Register WDT_ST 0x5041 8 bits D7 2 reserved 0 when being read D1 WDTMD NMI Reset mode select 1 Reset 0...

Страница 107: ...no parity Stop bit 1 or 2 bits Start bit 1 bit fixed Supports full duplex communications Includes a 2 byte receive data buffer and a 1 byte transmit data buffer Includes a baud rate generator with fi...

Страница 108: ...n from the initial value set via software and outputs an underflow signal when the counter underflows The underflow signal is used to generate the transfer clock The un derflow cycle can be programmed...

Страница 109: ...setting 0 to 255 bps Transfer rate bit s FMD FMD 3 0 fine mode setting 0 to 15 Note The UART transfer rate is capped at 230 400 bps 115 200 bps in IrDA mode Do not set faster transfer rates Fine Mode...

Страница 110: ...bit length to 1 bit Setting STPB to 1 configures it to 2 bits Parity bit Whether the parity function is enabled or disabled is selected by PREN UART_MODx register Setting PREN to 0 default disables t...

Страница 111: ...egister The TDBE flag indicates the transmit data buffer status This flag switches to 0 when the application program writes data to the transmit data buffer and reverts to 1 when the buffer data is se...

Страница 112: ...ontents once This resets the RDRY flag The buffer reverts to state 1 above If the receive data buffer contents are read twice the second data read will be invalid 3 RDRY 1 RD2B 1 Two 8 bit data have b...

Страница 113: ...1 parity enabled data received is checked for parity Data received in the shift register is checked for parity when sent to the receive data buffer The matching is checked against the PMD UART_MODx r...

Страница 114: ...er routine to determine whether the UART interrupt is attributable to an end of transmission If TRED is 1 the transmission processing can be terminated Receive buffer full interrupt To use this interr...

Страница 115: ...and the Low pulse width is converted to 16 sclk16 cycles before entry to the receive shift register The demodulator circuit uses the pulse detection clock selected separately from the transfer clock...

Страница 116: ...RMD All UART_BRx register bits BR 7 0 All UART_FMDx register bits FMD 3 0 All UART_CLKx register bits UTCLKD 1 0 UTCLKSRC 1 0 UTCLKE UART Ch x Status Register UART_STx Register name address Bit name F...

Страница 117: ...e data buffer contains two received data 1 R Second byte can be read 0 R Second byte not received default RD2B is set to 1 when the second byte of data is loaded into the receive data buffer and is re...

Страница 118: ...buffer The receive data buffer is a 2 byte FIFO that allows proper data reception until it fills even if data is not read out If the buffer is full and the shift register also contains received data...

Страница 119: ...ive error int enable 1 Enable 0 Disable 0 R W D5 RIEN Receive buffer full int enable 1 Enable 0 Disable 0 R W D4 TIEN Transmit buffer empty int enable 1 Enable 0 Disable 0 R W D3 2 reserved 0 when bei...

Страница 120: ...s the transmit data buffer UART Ch x Expansion Register UART_EXPx Register name address Bit name Function Setting init R W Remarks UART Ch x Expansion Register UART_EXPx 0x4105 8 bits D7 1 reserved 0...

Страница 121: ...0x6 D D D D D D 0x7 D D D D D D D 0x8 D D D D D D D D 0x9 D D D D D D D D D 0xa D D D D D D D D D D 0xb D D D D D D D D D D D 0xc D D D D D D D D D D D D 0xd D D D D D D D D D D D D D 0xe D D D D D D...

Страница 122: ...1 Default 0x0 D 3 2 UTCLKSRC 1 0 Clock Source Select Bits Selects the count clock source for the baud rate generator 9 4 Clock Source Selection Table 14 uTClKSRC 1 0 Clock source 0x3 External clock SC...

Страница 123: ...uffer 1 byte SDIx PCLK Internal bus ITC SPI Ch x Bus I F and control registers SPICLKx SPISSx Shift register Transmit data buffer 1 byte Clock transfer control SDOx T8 Ch 0 output clock Interrupt cont...

Страница 124: ...rmation on T8 control see the 8 bit timer T8 chapter PCLK 8 bit timer Ch 0 output clock or PCLK 4 SPI clock SPICLKx output 3 1 Master Mode SPI Clock Figure 15 In slave mode the SPI clock is input via...

Страница 125: ...gister is shifted in sequence at the clock rising or falling edge as determined by CPHA SPI_CTLx register and CPOL SPI_CTLx register see Figure 15 4 1 and sent from the SDOx pin Note Make sure that SP...

Страница 126: ...in sequence in the shift register at the rising or falling edge of the clock determined by CPHA SPI_CTLx register and CPOL SPI_CTLx register See Figure 15 4 1 The received data is loaded into the rec...

Страница 127: ...ause will not be sent to the ITC When transmit data written to the transmit data buffer is transferred to the shift register the SPI module sets SPTBE SPI_STx register to 1 indicating that the transmi...

Страница 128: ...he SPI transfer status 1 R Operating 0 R Standby default SPBSY is set to 1 when the SPI starts data transfer in master mode and is maintained at 1 while transfer is underway It is cleared to 0 once th...

Страница 129: ...SPRDB7 MSB SPRDB0 LSB 0x0 to 0xff 0x0 R D 15 8 Reserved D 7 0 SPRDB 7 0 SPI Receive Data Buffer Bits Contains the received data Default 0x0 SPRBF SPI_STx register is set to 1 data full as soon as dat...

Страница 130: ...e Bit Enables or disables SPI transmit data buffer empty interrupts 1 R W Enabled 0 R W Disabled default Setting SPTIE to 1 enables the output of SPI interrupt requests to the ITC due to a transmit da...

Страница 131: ...nal clock In slave mode data is transferred by inputting the clock from the master device D0 SPEN SPI Enable Bit Enables or disables SPI module operation 1 R W Enabled 0 R W Disabled default Setting S...

Страница 132: ...functions LFRO signal output frame interrupt Figure 16 1 1 shows the LCD driver and drive power supply configuration COMx SEGx LFRO DSPAR DSPC 1 0 LDUTY 2 0 FRMCNT 1 0 DSPREV To ITC Frame interrupt r...

Страница 133: ...SC1A clock is used as LCLK after dividing by 64 typ 512 Hz When the clock source is OSC3B When OSC3B is selected for the clock source use LCDTCLKD 1 0 LCD_TCLK register to select the di vision ratio 3...

Страница 134: ...duty 0x2 fOSC3B LCDTCLKD 6 fOSC3B LCDTCLKD 9 fOSC3B LCDTCLKD 12 fOSC3B LCDTCLKD 15 1 2 duty 0x1 fOSC3B LCDTCLKD 4 fOSC3B LCDTCLKD 8 fOSC3B LCDTCLKD 12 fOSC3B LCDTCLKD 16 Static 0x0 fOSC3B LCDTCLKD 4...

Страница 135: ...ding to the duty selections 0 1 2 3 0 1 2 3 LFRO COM0 COM1 VDD VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS COM2 VC3 VC2 VC1 VSS COM3 VC3 VC2 VC1 VSS COM0 1 2 3 SEGx VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1...

Страница 136: ...RO COM0 COM1 VDD VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS COM2 VC3 VC2 VC1 VSS COM0 1 2 SEGx VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS SEGx 1 frame Fra...

Страница 137: ...VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS SEGx 1 frame Frame interrupt Frame interrupt LCD display status Off On 4 2 3 1 2 Duty Drive Waveform Figure 16 0 0 LFRO COM0 1 frame Frame i...

Страница 138: ...G13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 5 1 Display Memory Map 1 4 duty Figure 16 Bit Address COM pin 0x53c0 0x53c1 0x53c2 0x53c...

Страница 139: ...For normal display set DSPC 1 0 to 0x1 Note that the clock must be supplied See Section 16 3 If Display off is selected the drive voltage supplied from the LCD power supply circuit stops and the VC1...

Страница 140: ...Table 16 address Register name Function 0x5070 LCD_TCLK LCD Clock Select Register Selects the LCD clock 0x50a0 LCD_DCTL LCD Display Control Register Controls the LCD display 0x50a2 LCD_CCTL LCD Clock...

Страница 141: ...required stop the clock to reduce current consumption LCD Display Control Register LCD_DCTL Register name address Bit name Function Setting init R W Remarks LCD Display Control Register LCD_DCTL 0x50...

Страница 142: ...0x2 0x1 0x0 1 16 1 12 1 8 1 4 D5 3 reserved 0 when being read D2 0 LDUTY 2 0 LCD duty select LDUTY 2 0 Duty 0x3 R W 0x7 0x4 0x3 0x2 0x1 0x0 reserved 1 4 1 3 1 2 Static D 7 6 FRMCNT 1 0 Frame Frequenc...

Страница 143: ...e Power Supply chapter LCD Interrupt Mask Register LCD_IMSK Register name address Bit name Function Setting init R W Remarks LCD Interrupt Mask Register LCD_IMSK 0x50a5 8 bits D7 1 reserved 0 when bei...

Страница 144: ...output pin Outputs the buzzer signal generated by the sound generator BZ O 1 Buzzer inverted output pin Outputs the inverted buzzer signal generated by the sound generator The SND module output pins...

Страница 145: ...ted from among eight types using BZDT 2 0 SND_BZDT register 4 2 1 Volume Level Settings Table 17 Volume level BZDT 2 0 Duty ratio by buzzer frequency hz 4096 0 3276 8 2730 7 2340 6 2048 0 1638 4 1365...

Страница 146: ...uzzer output and setting it to 0 stops the output The buzzer frequency setting with BZFQ 2 0 and volume setting with BZDT 2 0 are both effective BZEN BZ output BZ output 1 0 0 5 2 1 Buzzer Output in N...

Страница 147: ...sted in Table 17 4 2 1 attenuation time selection The envelope attenuation time time to change the duty ratio can be selected from among four types using BZTM 1 0 SND_CTL register 5 4 1 Envelope Atten...

Страница 148: ...name Function Setting init R W Remarks SND Clock Control Register SND_CLK 0x506e 8 bits D7 1 reserved 0 when being read D0 SNDCLKE SND clock enable 1 Enable 0 Disable 0 R W D 7 1 Reserved D0 SNDCLKE S...

Страница 149: ...x0 Normal mode Buzzer output is turned on and off via software Default 0x0 D1 Reserved D0 BZEN Buzzer Output Control Bit Controls buzzer output 1 R W On Trigger 0 R W Off default Normal mode Setting B...

Страница 150: ...unction Setting init R W Remarks Buzzer Duty Ratio Control Register SND_BZDT 0x5182 8 bits D7 3 reserved 0 when being read D2 0 BZDT 2 0 Buzzer duty ratio select BZDT 2 0 Duty volume 0x0 R W 0x7 0x0 L...

Страница 151: ...18 Comparison Voltage Setting 18 2 The SVD circuit compares the power supply voltage VDD against the comparison voltage set by software and out puts results indicating whether the power supply voltag...

Страница 152: ...Register name Function 0x5100 SVD_EN SVD Enable Register Enables disables the SVD operation 0x5101 SVD_CMP SVD Comparison Voltage Register Sets the comparison voltage 0x5102 SVD_RSLT SVD Detection Re...

Страница 153: ...one of 13 comparison voltages for detecting voltage drops 4 2 Comparison Voltage Settings Table 18 SVDC 4 0 Comparison Voltage SVDC 4 0 Comparison Voltage 0x1f Reserved 0xf 2 08 V 0x1e 0xe 1 98 V 0x1d...

Страница 154: ...Reserved D0 SVDDT SVD Detection Result Bit Indicates the power supply voltage detection results 1 R Power supply voltage VDD comparison voltage 0 R Power supply voltage VDD comparison voltage The SVD...

Страница 155: ...t Flag output Operation result 1 1 Multiplier Divider Block Diagram Figure 19 Operation Mode and Output Mode 19 2 The Multiplier divider operates according to the operation mode specified by the appli...

Страница 156: ...n mode Performs unsigned multiplication 0x5 Signed multiplication mode Performs signed multiplication 0x6 Reserved 0x7 Signed MAC mode Performs signed MAC operation 0x8 Unsigned division mode Performs...

Страница 157: ...ation mode to 0x8 unsigned division or 0x9 signed division Then send the 16 bit dividend B and 16 bit divisor C to the multiplier divider using a ld ca instruction The quotient and the residue will be...

Страница 158: ...elector Argument 2 Argument 1 16 bits 32 bits Coprocessor output 16 bits Flag output 5 1 Data Path in Initialize Mode Figure 19 5 1 Initializing the Operation Result Register Table 19 Mode setting val...

Страница 159: ...operation result read mode and 16 high order bits output mode ld ca r1 r0 Loads the 16 high order bits of the result to r1 Conditions to set the overflow V flag An overflow occurs in a MAC operation a...

Страница 160: ...to operation result read mode The operation result register keeps the loaded operation result until it is rewritten by other operation S1C17 Core Operation result register Selector Argument 2 Argument...

Страница 161: ...ave the VC1 to VC3 CA and CB pins open Current Consumption 20 3 Unless otherwise specified VDD 2 0 to 3 6V VSS 0V Ta 25 C PCKEN 1 0 0x3 ON RDWAIT 1 0 0x0 no wait CCLKGR 1 0 0x0 gear ratio 1 1 RTCRUN 0...

Страница 162: ...mption temperature characteristic Current consumption temperature characteristic during execution with OSC1a clock gear during execution with OSC3B clock gear OSC1A 32 768kHz crystal OSC3B OFF OSC3B O...

Страница 163: ...y accuracy per 1 C change in temperature with reference to 25 C 0 05 0 07 C 1 Reference value external Clock input Characteristics 20 5 EXCLx tECH tECL tCF tCR VIH VIL SCLKx tCF tCR VIH VIL Unless oth...

Страница 164: ...c Ta 85 C Max value Ta 85 C Min value 0 0 0 2 4 6 8 10 12 14 16 18 0 2 0 4 0 6 0 8 1 0 VDD VOH V I OH mA VDD 2 0 V VDD 3 6 V 0 0 10 9 8 7 6 5 4 3 2 1 0 I OL mA VOL V 0 2 0 4 0 6 0 8 1 0 VDD 2 0 V VDD...

Страница 165: ...Unless otherwise specified VDD 2 2 to 3 6V VSS 0V Ta 25 C C2 C5 0 1 F Checker pattern displayed No panel load VCSEL 1 VC2 reference voltage LCD_BCLK 1 0 0x1 2kHz OSC1A 32kHz source clock FRMCNT 1 0 0x...

Страница 166: ...0 3 5 4 0 lCD drive voltage temperature characteristic lCD drive voltage load characteristic VDD 3 0V LCD_BCLK 1 0 0x1 2kHz OSC1A 32kHz VDD 2 2V VC2 reference VDD 1 8V VC1 reference source clock FRMC...

Страница 167: ...frame frequency dependence current consumption characteristic VDD 3 0V Ta 25 C LCD_BCLK 1 0 0x1 2kHz OSC1A 32kHz source clock FRMCNT 1 0 0x0 to 0x3 128 to 32Hz OSC1A 32kHz LCLK 512Hz LDUTY 2 0 0x3 1...

Страница 168: ...0 0x14 2 58 V SVDC 4 0 0x15 2 68 V SVDC 4 0 0x16 2 78 V SVDC 4 0 0x17 2 88 V SVDC 4 0 0x18 2 98 V SVDC 4 0 0x19 3 08 V SVDC 4 0 0x1a 3 18 V SVDC 4 0 0x1b V SVDC 4 0 0x1c V SVDC 4 0 0x1d V SVDC 4 0 0x...

Страница 169: ...illator circuit Symbol name Recommended part X tal1 32 kHz crystal resonator C 002RX R1 50 kW Max CL 7 pF manufactured by SEIKO EPSON Other Symbol name Recommended value CP Capacitor for power supply...

Страница 170: ...COM1 7 SEG27 39 COM0 8 SEG26 40 N C 9 SEG25 41 VC3 10 SEG24 42 VC2 11 SEG23 43 VC1 12 SEG22 44 CB 13 SEG21 45 CA 14 SEG20 46 VSS 15 SEG19 47 VDD 16 SEG18 48 VD1 17 SEG17 49 OSC1 18 SEG16 50 OSC2 19 SE...

Страница 171: ...1 CT_CNT Clock Timer Counter Register Counter data 0x5002 CT_IMSK Clock Timer Interrupt Mask Register Enables disables interrupt 0x5003 CT_IFLG Clock Timer Interrupt Flag Register Indicates resets int...

Страница 172: ...ister Selects the P1 3 0 port functions MISC registers 16 bit device 0x5324 MISC_PROT MISC Protect Register Enables writing to the MISC registers 0x5328 MISC_TTBRL Vector Table Address Low Register Se...

Страница 173: ...PMD Parity mode select 1 Odd 0 Even 0 R W D1 STPB Stop bit select 1 2 bits 0 1 bit 0 R W D0 reserved 0 when being read UART Ch 0 Control Register UART_CTL0 0x4104 8 bits D7 TEIEN End of transmission...

Страница 174: ...4314 Interrupt Controller Register name address Bit name Function Setting init R W Remarks Interrupt Level Setup Register 0 ITC_LV0 0x4306 16 bits D15 3 reserved 0 when being read D2 0 ILV0 2 0 P0 int...

Страница 175: ...rrupt Mask Register CT_IMSK 0x5002 8 bits D7 4 reserved 0 when being read D3 CTIE32 32 Hz interrupt enable 1 Enable 0 Disable 0 R W D2 CTIE8 8 Hz interrupt enable 1 Enable 0 Disable 0 R W D1 CTIE2 2 H...

Страница 176: ...CLG_WAIT 0x507d 8 bits D7 6 OSC3BWT 1 0 OSC3B stabilization wait cycle select OSC3BWT 1 0 Wait cycle 0x0 R W 0x3 0x2 0x1 0x0 8 cycles 16 cycles 32 cycles 64 cycles D5 2 reserved 0 when being read D1 0...

Страница 177: ...n being read D2 0 LDUTY 2 0 LCD duty select LDUTY 2 0 Duty 0x3 R W 0x7 0x4 0x3 0x2 0x1 0x0 reserved 1 4 1 3 1 2 Static LCD Voltage Regulator Control Register LCD_VREG 0x50a3 8 bits D7 5 reserved 0 whe...

Страница 178: ...0 Frequency 0x0 R W 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 1170 3 Hz 1365 3 Hz 1638 4 Hz 2048 0 Hz 2340 6 Hz 2730 7 Hz 3276 8 Hz 4096 0 Hz Buzzer Duty Ratio Control Register SND_BZDT 0x5182 8 bits D7 3 rese...

Страница 179: ...1 Port Input Data Register P1_IN 0x5210 8 bits D7 4 reserved 0 when being read D3 0 P1IN 3 0 P1 3 0 port input data 1 1 H 0 0 L R P1 Port Output Data Register P1_OUT 0x5211 8 bits D7 4 reserved 0 when...

Страница 180: ...0 R W 0x3 0x2 0x1 0x0 reserved BZ P11 reserved D1 0 P10MUX 1 0 P10 port function select P10MUX 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved SPICLK0 FOUTB P10 0x5324 0x532c MISC Registers Register nam...

Страница 181: ...0 W 0 when being read D0 PRUN Counter run stop control 1 Run 0 Stop 0 R W T16A Counter Ch 0 Data Register T16A_TC0 0x5402 16 bits D15 0 T16ATC 15 0 Counter data T16ATC15 MSB T16ATC0 LSB 0x0 to 0xffff...

Страница 182: ...BCDMD BCD mode select 1 BCD mode 0 Binary mode 0 R W D4 RTC24H 24H 12H mode select 1 12H 0 24H 0 R W D3 1 reserved 0 when being read D0 RTCRUN RTC run stop control 1 Run 0 Stop 0 R W RTC Interrupt Ena...

Страница 183: ...echnical Manual Seiko Epson Corporation AP A 13 Rev 1 0 0xffff84 S1C17 Core I O Register name address Bit name Function Setting init R W Remarks Processor ID Register IDIR 0xffff84 8 bits D7 0 IDIR 7...

Страница 184: ...k source You can reduce current consumption by selecting the OSC1A clock when low speed processing is possible Disable unnecessary oscillator circuits CLG module Operate the oscillator comprising the...

Страница 185: ...top Run Stop Execute slp instruction 1 2 Oscillation for RTC Stop Stop Stop Run Stop Execute halt instruction 1 2 Oscillation system CLK Stop Stop Stop Run Run Execute halt instruction 1 2 3 Oscillati...

Страница 186: ...rn on only if operations are unstable lCD power supply circuit Setting VCSEL to 0 VC1 reference voltage will increase current consumption Set VCSEL to 1 VC2 reference voltage if the power supply volta...

Страница 187: ...ated wiring including wiring for adjacent circuit board lay ers Layers wired should be adequately shielded as much as possible Fully ground adjacent layers where possible At minimum shield the area at...

Страница 188: ...olatile memory data retention characteristics before prod uct delivery if the product is subjected to heat stress exceeding regular reflow conditions during mounting processes unused pins 1 I O port P...

Страница 189: ...perly taking noise measures into consideration For the recommended patterns on the circuit board see Mounting Precautions in Appendix noise Measures for interrupt input Pins This product is able to ge...

Страница 190: ..._0_handler 0x0b 0x2c T16A2 ch0 long int0c_handler 0x0c 0x30 long int0d_handler 0x0d 0x34 long t8_0_handler 0x0e 0x38 T8 ch0 long int0f_handler 0x0f 0x3c long uart_0_handler 0x10 0x40 UART ch0 long int...

Страница 191: ...section is declared to locate the vector table in the vector section 2 Interrupt handler routine addresses are defined as vectors intXX_handler can be used for software interrupts 3 The program code...

Страница 192: ...fferences in the detection voltage Typ values Electrical characteristics The characteristic values are not the same due to dif ferences in manufacturing process Package chip TQFP14 80pin Aluminum pad...

Страница 193: ...ReViSiOn hiSTORY Revision history Code no Page Contents 412495700 All New establishment...

Страница 194: ...henzhen 518057 CHINA Phone 86 755 2699 3828 Fax 86 755 2699 3838 EPSON HONG KONG LTD Unit 715 723 7 F Trade Square 681 Cheung Sha Wan Road Kowloon Hong Kong Phone 852 2585 4600 Fax 852 2827 4346 EPSON...

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