Programming Information
61
Table 3.5.26: Loop Gain Register Definition
The following formulas and steps are used to calculate the loop gain register val-
ue:
1.
Calculate the value for Loop Gain (LG):
For the 4430-V LG = (LBW/Demod f
c
) x 12750
For the 4430-VN LG = (LBW/Demod f
c
) x (5.1 x 10
5
)
Where LBW is the loop bandwidth selected in
Section 3.5.17
Register 38h
(71h), Loop Capacitor/Input Select on page 54
and Demod fc is the demodula-
tor carrier frequency input by the user in
Section 3.3
.
2.
Round the results of Step 1.
3.
If the results of Step 1 are less than 40, write a 28h to register 35h. If the results
are greater than 40, convert the number to a hexadecimal number and write
it to the register. If the value is larger than 255, write a FFh to register 35h.
Programming
Example
For the programming example given, the following steps apply:
1.
Calculating the value for LG for the 4430-VN:
LG = (LBW/Demod f
c
) x (5.1 x 10
5
)
LG = (4/8000) x (5.1 x 10
5
) = 255
2.
Rounding the results of Step 1 results in LG = 255.
A value of FFh is written to register 35h.
3.5.21 Register 39h (73h), Input High Pass Filter Tuning
This register selects the demodulator input high pass filter setting.
Figure 3.5.21
illustrates the breakout of register bit assignments.
Bit No.
Bit Name(s)
Functional Description
07-00
Loop Gain
(Set according to the formulas that follow)
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