Programming Information
55
determined.
Table 3.5.22: E
b
/N
0
vs. Maximum LPSR
5.
The loop bandwidth value is then divided by the square root of the
demodulator frequency.
6.
The results are compared to the values from
Table 3.5.23, “Loop Capacitor
Selection,” on page 55
. The loop bandwidth capacitor select bits are then
determined.
Note:
The table has different selections for the 4430-VN mod-
el versus the 4430-V model.
Table 3.5.23: Loop Capacitor Selection
7.
Select the input source and mode for the demodulator.
8.
Arrange the bits per
Table 3.5.21, “Loop Capacitor Input Source/Mode Register
Definition,” on page 54
and write the value to the register.
Programming
Example
Following the steps listed above:
1.
From
Section 3.5
Register Programming on page 31
the user value for Eb/No
was selected as 8dB.
2.
A LPSR value is selected from
Table 3.5.22, “Eb/N0 vs. Maximum LPSR,” on
page 55
.
LPSR = 0.02
E
b
/N
0
LPSR
E
b
/N
0
LPSR
-4
0.00003
6
0.007
-3
0.00005
7
0.015
-2
0.0008
8
0.02
-1
0.00014
9
0.035
0
0.00024
10
0.06
1
0.0003
11
0.1
2
0.0006
12
0.15
3
0.001
13
0.2
4
0.002
14
0.3
5
0.004
-
-
Range for 4430-V
LBW/Demod f
c
Range for 4430-VN LBW/De-
mod f
c
4430-V
Cap (C)
4430-VN
Cap (C)
Reg. 38h
Bits 2-0
Range: (15 to 50)
Range: (.05 to 3)
1.5
x
10
-10
2.2
x
10
-9
000b
Range: (3 to15)
Range: (0.1 to 0.5)
6.8
x
10
-9
3.9
x
10
-8
001b
Range: (0.5 to 3)
Range: (0.015 to 0.1)
2.2
x
10
-7
6.8
x
10
-7
011b
Range: (0.03 to 0.5)
Range: (1.5
x
10
-3
to 0.015)
1.1
x
10
-5
5.0
x
10
-5
100b
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