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4430-V & VN BPSK/QPSK VME Demodulator & Optional Modulator User’s Manual
Doc: 4430_V,VN.fm, © 11 Jul 2005, 14:55
Initially, set register 3Eh to 128. Read back the value in register 33h. It should
read 128 + 12. If the number is too high, you should step register 3Eh down one
increment at a time while reading back register 33h. Likewise, if the value is to
low, you should decrement the value in register 3Eh while reading the value in
register 33h. A delay of greater than (1/(2
x
p
x
loop bandwidth)) should be al-
lowed between each step to allow the loop to settle. If it is not desired to use a
programmed delay between the read and write functions, bit 2 of register 32h
can be polled to determine if the loop stress value conversion is complete.
If register 3Eh is stepped to the maximum value of 255 or minimum of 0 and is
still not within the tolerance, then set the register 80h.
Programming
Example
Following the steps described above:
1.
Set the register in the default state:
Register 3Eh = 80h
2.
Delay while waiting for the loop to settle:
Settling Delay = 1/(2 x p x loop bandwidth)
Settling Delay = (1/125.7) = 0.00795 seconds = 7.95 milliseconds
3.
Read the status in register 33h:
Assume register 33h = 8Fh
4.
Evaluate the results to determine if the value is within the range 128 ± 12.
Assuming register 33h = 8Fh = 143.
Since this value is greater than 128 + 12, register 3Eh will require decrementing
5.
Increment or decrement the value written to register 3Eh as necessary:
Register 3Eh = 7Fh
6.
Repeat
Step 2
through
Step 5
until the value in register 33h is within the 128
10
(± 12
10
) desired value or until the value written to register 3Eh is equal to 00h
or FFh.
7.
If the value written to register 3Eh is equal to 00h or FFh write 80h to the
register.
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