RTD Embedded Technologies, Inc.
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28
DM35425HR User’s Manual
The following table list the key digital codes and corresponding output voltages for the DAC converters.
DAC Bit Weight
Ideal Output Voltages (mV)
-5 to +5 V 0 to +5 V -10 to +10 V 0 to +10 V
1111 1111 1111
+4997.56 +4998.78
+9995.12
+9997.56
1000 0000 0000
0 +2500.00
0000.00
+5000.00
0100 0000 0000
-2500.00 +1250.00
-5000.00
+2500.00
0010 0000 0000
-3750.00
+625.00
-7500.00
+1250.00
0001 0000 0000
-4375.00
+312.50
-8750.00
+625.00
0000 1000 0000
-4687.50
+156.25
-9375.00
+312.50
0000 0100 0000
-4843.75
+78.13
-9687.50
+156.25
0000 0010 0000
-4921.88
+39.06
-9843.75
+78.13
0000 0001 0000
-4960.94
+19.53
-9921.88
+39.06
0000 0000 1000
-4980.47
+9.77
-9960.94
+19.53
0000 0000 0100
-4990.24
+4.88
-9980.47
+9.77
0000 0000 0010
-4995.12
+2.44
-9990.23
+4.88
0000 0000 0001
-4997.56
+1.22
-9995.12
+2.44
0000 0000 0000
-5000.00
0.00
-10000.00
0.00
Voltage values for each bit will vary depending mode and gain. The formula for calculating count value as follows:
Bipolar Range
Unipolar Range
𝐶𝑜𝑢𝑛𝑡 = (
𝑉𝑜𝑙𝑡𝑎𝑔𝑒
𝐺𝑎𝑖𝑛
+ 5
10
) ×2
12
𝐶𝑜𝑢𝑛𝑡 = (
𝑉𝑜𝑙𝑡𝑎𝑔𝑒
𝐺𝑎𝑖𝑛
10
) ×2
12
Refer to
on page 44 for full-scale ranges for both unipolar and bipolar modes.
Each DAC converter has a 511 sample FIFO for DMA. Each sample is packed into 32 bits, right justified and sign-extended.
5.5
Advanced Digital I/O
The DM35425 features 32 digital I/O line with DMA, parallel bus mode, and advance interrupts.
DMA
The DM35425 has three DMA channels for Digital I/O: input, output, and direction. Each channel has a 511 sample FIFO for DMA. Each
sample is packed into 32 bits.
Advanced Interrupts
The DM35425 has an advanced interrupt block that can generate an interrupt on a match or event. The interrupts are across all 32 digital I/O.
The bits can be individually selected.
When an interrupt is generated, the data on all of the ports is latched into the Capture registers. Bits are tested regardless of if a pin is an input
or output.
A Match interrupt is generated when all un-masked bits in the Compare register match the input value of the port. An Event interrupt is
generated when any un-masked input port bit changes.
Parallel Bus Mode
The DM35425 also features parallel bus mode for the digital I/O lines. In this mode, the 3 MSB lines of the Digital I/O are switched to control
signals: Ready, Valid, and Clock. The remaining lines are used as a data bus.
When the clock pin is set to output, a high clock pulse (50ns) will be sent every Digital I/O pacer clock. Also, at the rising edge of each clock
pulse, data in the OUT FIFO will be outputted on all digital I/O set to output.
The Valid pin is set high when the valid pin is set to an output and the Out FIFO is not empty.
When the clock pin is set to input, when the clock pin receives a rising edge and the valid pin is high all 32 bits on data will be written to the IN
FIFO.
