RTD Embedded Technologies, Inc.
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50
DM35425HR User’s Manual
B[29]: P_BUS_VALID: When set high, this will output high valid signal once the Digital I/O DMA OUTPUT FIFO is setup and started.
When using the module to receive data, set this bit low to receive the valid signal.
B[28:0]: P_BUS_DATA: Sets the direction of the I/O bit. 0=input, 1=output.
6.5.19
ADV_INT_MODE
(R
EAD
/W
RITE
)
Set the current mode for the advance interrupts.
B[1:0]: Mode
o
0x0: Disabled. This is the power-on state. In this mode no advanced interrupts will occur.
o
0x1: Match. A Match interrupt is generated when all un-masked bits in the Compare register match the input value of the
port. This is when the following expression is true:
((DIO_INPUT xor ADV_INT_COMP) and not ADV_INT_MASK
) = ‘0’
o
0x2: Event Mode. An Event interrupt is generated when any un-masked input port bit changes. This is when the following
expression is:
((DIO_INPUT xor ADV_INT_ CAPT) and not ADV_INT_MASK
) = ‘1’
The ADV_INT_CAPT register is updated at every advanced interrupt or event.
6.5.20
ADV_INT_MASK
(R
EAD
/W
RITE
)
This register determines if a bit is checked for the advanced interrupts.
0 = Bit is used for match/event 1 = Bit is ignored
6.5.21
ADV_INT_COMP
(R
EAD
/W
RITE
)
The compare register is used for the Match interrupt. When all selected bits in this register match all selected bits on the DIO_INPUT register,
an interrupt is generated.
6.5.22
ADV_INT_CAPT
(R
EAD
/W
RITE
)
The Capture register latches the input ports when an interrupt is generated. All values are latched, regardless of the ADV_INT_MASK register,
or DIO_DIRECTION.
This register can be written to when ADV_INT_MODE is set to Disabled.
6.5.23
P_BUS_EN
(R
EAD
/W
RITE
)
The P_BUS_EN register is used to enable the parallel bus feature of the digital I/O.
0 = Disabled
1 = Enabled
6.5.24
P_BUS_READY_EN
(R
EAD
/W
RITE
)
The P_BUS_READY_EN register is used to enable the parallel bus ready signal check of the digital I/O. When this bit is enabled the
P_BUS_CLK will not be outputted until P_BUS_READY is high.
0 = Disabled
1 = Enabled
6.5.25
CH_FIFO_ACCESS
(R
EAD
/W
RITE
)
This register provides direct access to the DMA FIFO. It can be used to access the data without the use of the DMA engine. The DMA engine
for this channel must be set to “Pause.”
Each register access advances to the next sample.
