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26
DM35425HR User’s Manual
The DM35425 also features an attenuator in the front-end. This allows for additional input range of
±
10V. This feature can only be used in
bipolar mode.
Refer to
on page 39 for full-scale ranges for both unipolar and bipolar modes.
Bipolar/Unipolar Mode
In bipolar mode the data is collected in two’s complement format. In this format the MSB of the data is the sign bit. If the MSB is “0” the output
data is positive value. If the MSB is “1” the output code is negative. The 1
2-bits of data are sign-extended into a 32-bit word before transferring
to the FIFO.
In unipolar mode there is no sign bit, since all values are po
sitive. When the output code is all “0” the input voltage is 0 volts. When the output
code is all “1” the input voltage is 10 volts when the gain is set to 1.
Voltage values for each bit will vary depending on input range. For example, if the input is set for ±5V, the formula for calculating voltage is as
follows:
𝑉𝑜𝑙𝑡𝑎𝑔𝑒 =
𝐼𝑛𝑝𝑢𝑡 𝑅𝑎𝑛𝑔𝑒
2
12
×𝐶𝑜𝑛𝑣𝑒𝑟𝑠𝑖𝑜𝑛 𝐷𝑎𝑡𝑎
𝑉𝑜𝑙𝑡𝑎𝑔𝑒 =
10
1 ×2
12
×𝐶𝑜𝑛𝑣𝑒𝑟𝑠𝑖𝑜𝑛 𝐷𝑎𝑡𝑎
𝑉𝑜𝑙𝑡𝑎𝑔𝑒 = 2.44𝑚𝑉×𝐶𝑜𝑛𝑣𝑒𝑟𝑠𝑖𝑜𝑛 𝐷𝑎𝑡𝑎
Table 12: ADC Bipolar Code ( ±5 V Input Range)
Input Voltages Sign
Output Code
+4.998 V
0
MSB 0111 1111 1111 LSB
+2.500 V
0
MSB 0100 0000 000 LSB
0.000 V
0
MSB 0000 0000 0000 LSB
-0.00244 V
1
MSB 1111 111 1111 LSB
-5.000 V
1
MSB 1000 0000 0000 LSB
Table 13: ADC Bipolar Code ( ±10 V Input Range)
Input Voltages Sign
Output Code
+9.995 V
0
MSB 0111 1111 1111 LSB
+5.000 V
0
MSB 0100 0000 000 LSB
0.000 V
0
MSB 0000 0000 0000 LSB
-0.00488 V
1
MSB 1111 111 1111 LSB
-10.000 V
1
MSB 1000 0000 0000 LSB
Table 14: ADC Unipolar Code ( 0 to 10 V Input Range)
Input Voltages
Sign
Output Code
+9.99756 V
0
MSB 1111 1111 1111 LSB
+5.000 V
0
MSB 1000 0000 000 LSB
0.000 V
0
MSB 0000 0000 0000 LSB
Channel Delay
The DM35425 uses a 32 single-ended/16 differential channel multiplexed input, when ADC is sampling, which iterates through each enabled
channels after the pervious channel has finished sampling. By default, there is no delay between channel sampling. The channel delay bits of
the
CHn_FRONT_END_CONFIG (Maskable Read/Write)
register on page 39 provide a way to delay sampling between channels. This is used
to reduce cross talk between channels. Refer to
on page 10 to see typical channel to channel cross talk.
Effective Sampling Rate
The DM35425 uses a multiplexed input to allow a max of 32 single-end/16-differential channels using one ADC. This module burst samples all
enabled channels after each pacer clock pulse, starting at the first enabled channel and sequentially every enabled channel afterwards. Due to
