ROHS MC9S08QE128, Справочное руководство

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Chapter 18 Debug Module (DBG) (128K)
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Freescale Semiconductor 329
18.3.3.8 Debug FIFO Low Register (DBGFL)
Table 18-9. DBGFH Field Descriptions
Field Description
Bits 15–8 FIFO High Data Bits — The FIFO High data bits provide access to bits [15:8] of data in the FIFO. This register
is not used in event only modes and will read a $00 for valid FIFO words.
Module Base + 0x0007
7 6 5 4 3 2 1 0
R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
POR
or non-
end-run
0 0 0 0 0 0 0 0
Reset
end-run
1
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
U U U U U U U U
= Unimplemented or Reserved
Figure 18-9. Debug FIFO Low Register (DBGFL)
Table 18-10. DBGFL Field Descriptions
Field Description
Bits 7–0 FIFO Low Data Bits — The FIFO Low data bits contain the least significant byte of data in the FIFO. When
reading FIFO words, read DBGFX and DBGFH before reading DBGFL because reading DBGFL causes the
FIFO pointers to advance to the next FIFO location. In event-only modes, there is no useful information in DBGFX
and DBGFH so it is not necessary to read them before reading DBGFL.