ROHS MC9S08QE128, Справочное руководство

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Internal Clock Source (S08ICSV3)
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Freescale Semiconductor 207
11.1.5.4
FLL Bypassed Interna
l Low Power (FBILP)
In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the internal reference clock. The BDC clock is not available.
11.1.5.5
FLL Bypassed Externa
l (FBE)
In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is
bypassed. The ICS supplies a clock derived from the external reference clock. The external reference clock
can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external
clock source. The BDC clock is supplied from the FLL.
11.1.5.6
FLL Bypassed Externa
l Low Power (FBELP)
In FLL bypassed external low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the external reference clock. The external reference clock can be an external crystal/resonator
supplied by an OSC controlled by the ICS, or it can be another external clock source. The BDC clock is
not available.
11.1.5.7 Stop (STOP)
In stop mode the FLL is disabled and the internal or external reference clocks can be selected to be enabled
or disabled. The BDC clock is not available and the ICS does not provide an MCU clock source.
11.2 External Signal Description
There are no ICS signals that connect off chip.
11.3 Register Definition
Figure 11-1 is a summary of ICS registers.
Table 11-1. ICS Register Summary
Name
7 6 5 4 3 2 1 0
ICSC1
R
CLKS RDIV IREFS IRCLKEN IREFSTEN
W
ICSC2
R
BDIV RANGE HGO LP EREFS ERCLKEN EREFSTEN
W
ICSTRM
R
TRIM
W
ICSSC
R DRST
DMX32
IREFST CLKST OSCINIT
FTRIM
W DRS