Rohm BD71837MWV, Руководство по конструкции

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Application Note BD71837MWV Platform Design Guide
© 2018 ROHM Co., Ltd.
No. 61AN002E Rev.001
May.2018
1. Introduction ................................................................................................................................................................................ 1
2. Revision History ......................................................................................................................................................................... 4
3. Features ..................................................................................................................................................................................... 5
3.1. Terminologies ...................................................................................................................................................................... 5
3.2. Reference Documents ........................................................................................................................................................ 5
3.3. PMIC futures ....................................................................................................................................................................... 6
4. General Design Considerations ................................................................................................................................................. 7
4.1. Package Dimension of BD71837MWV ............................................................................................................................... 7
4.2. Pin Configuration ................................................................................................................................................................ 8
4.3. General Stack-up Recommendations ................................................................................................................................. 9
4.4. 6-layer Board Stack-up ....................................................................................................................................................... 9
4.5. Via Guidelines ................................................................................................................................................................... 10
4.6. Placement of PTHs underneath the exposed pad.............................................................................................................. 11
4.7. Outline for PCB layout ...................................................................................................................................................... 12
5. Platform Power Delivery Guidelines ......................................................................................................................................... 18
5.1. Platform Power Delivery ................................................................................................................................................... 18
5.2. General Layout Guideline ................................................................................................................................................. 20
5.2.1. Overall Component Placement .................................................................................................................................. 20
5.2.2. Large Current Loop .................................................................................................................................................... 21
5.2.3. Power GND ................................................................................................................................................................ 22
5.2.4. VSYS (Power supply for BD71837MWV analog circuit) ............................................................................................ 22
5.2.5. Other Signal Pattern Precautions .............................................................................................................................. 22
5.2.6. Feedback Sense Lines .............................................................................................................................................. 22
5.2.7. AGND layout .............................................................................................................................................................. 23
5.3. BUCK Convertors ............................................................................................................................................................. 24
5.3.1. BUCK1 (VDD_SoC) ................................................................................................................................................... 24
5.3.1.1. Schematic Example ............................................................................................................................................... 24
5.3.1.2. Schematic checklist ................................................................................................................................................ 24
5.3.1.3. Parts placement for each decoupling capacitor ...................................................................................................... 25
5.3.2. BUCK2 (VDD_ARM) .................................................................................................................................................. 25
5.3.2.1. Schematic Example ............................................................................................................................................... 25
5.3.2.2. Schematic checklist ................................................................................................................................................ 26
5.3.2.3. Layout Example ..................................................................................................................................................... 26
5.3.3. BUCK3 (VDD_GPU) .................................................................................................................................................. 27
5.3.3.1. Schematic Example ............................................................................................................................................... 27
5.3.3.2. Schematic Checklist ............................................................................................................................................... 27
5.3.3.3. Layout Example ..................................................................................................................................................... 28
5.3.4. BUCK4 (VDD_VPU) .................................................................................................................................................. 29
5.3.4.1. Schematic Example ............................................................................................................................................... 29
5.3.4.2. Schematic Checklist ............................................................................................................................................... 29
5.3.4.3. Layout Example ..................................................................................................................................................... 30
5.3.5. BUCK5 (VDD_DRAM) ............................................................................................................................................... 30