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Application Note 

BD71837MWV Platform Design Guide 

© 2018 ROHM Co., Ltd.

 

No. 61AN002E Rev.001

 

May.2018

 

5.2.7.  AGND layout 

 

 

AGND is recommended not 

to be connected to PGND for PMIC (exposed pad) directly to avoid noise effect. It’s better to short AGND 

to a GND at inner GND plane (stable GND) through PTH. 

The reference layout as above can be referred to. 

 

 

Figure 5.6 Connection between Power GND and Analog GND

 

Содержание BD71837MWV

Страница 1: ...ied BD71837MWV Platform Design Guide provides the guideline for designing PCB including recommendation for the PCB layer stack up the components placement and the PCB routings To reduce the risk that...

Страница 2: ...Layout Guideline 20 5 2 1 Overall Component Placement 20 5 2 2 Large Current Loop 21 5 2 3 Power GND 22 5 2 4 VSYS Power supply for BD71837MWV analog circuit 22 5 2 5 Other Signal Pattern Precautions...

Страница 3: ...mple 36 5 3 8 2 Schematic Checklist 36 5 3 8 3 Layout Example 37 5 4 LDOs 38 5 4 1 LDO1 NVCC_SNVS 38 5 4 2 LDO2 VDD_SNVS 38 5 4 3 LDO3 VDDA_1P8 VDDA_DRAM 38 5 4 4 LDO4 VDDA_0P9 38 5 4 5 LDO5 1P8_PHY 3...

Страница 4: ...ation Note BD71837MWV Platform Design Guide 2018 ROHM Co Ltd No 61AN002E Rev 001 May 2018 2 Revision History Table 2 1 Revision History Revision Number Description Revision Date 001 Initial release Ma...

Страница 5: ...Circuit FET Field Effect Transistor I2C Inter Integrated Circuit IRQ Interrupt ReQuest LDO Low Drop Out Regulator OCP Over Current Protection OVP Over Voltage Protection SoC System On a Chip 3 2 Refer...

Страница 6: ...Buck2 0 7V 1 3V 10mV step DVS IOMAX 4 0A Buck3 0 7V 1 3V 10mV step DVS IOMAX 2 1A Buck4 0 7V 1 3V 10mV step DVS IOMAX 1 0A Buck5 0 7V 1 35V 8 steps IOMAX 2 5A Buck6 3 0V 3 3V 100mV step IOMAX 3 0A Bu...

Страница 7: ...N002E Rev 001 May 2018 4 General Design Considerations This chapter provides general PCB design guidelines such as BD71837MWV general parts placement 4 1 Package Dimension of BD71837MWV Figure 4 1 The...

Страница 8: ...LX BUCK7_VIN BUCK7_FB IRQ_B POR_B C32K_OUT DVDD EXP PAD EXP PAD LDO3_FB VIN_3P3 LDO3_VOUT VSYS3 BUCK4_FB BUCK4_VIN BUCK4_LX BUCK3_LX BUCK3_LX BUCK3_VIN BUCK3_FB AGND INTLDO1P5 LDO7_VOUT VSYS1 XIN XOUT...

Страница 9: ...Mils thick copper It is recommended I2C signals to have the reference versus solid planes over the length of their routing and not to cross plane splits Ground should be the ideal reference The extra...

Страница 10: ...ability and electrical characteristics Type 3 PCB technology employs plated through hole PTH vias for breakout routing The dimension of PTH vias may vary as necessary Table 2 1 shows the recommended v...

Страница 11: ...issue it is highly recommended to keep the positons of PTHs away from the edge of the exposed pad by 500 m or more and PTHs should be placed not to disrupt the current flows between each GND of the o...

Страница 12: ...tom layer are shown in Figure 4 6 to Figure 4 11 The layout is designed supposing the position of the SoC as Figure 4 6 1st pin of SoC is positioned at lower right BUCK8 BUCK5 BUCK1 MUXSW BUCK7 BUCK2...

Страница 13: ...td No 61AN002E Rev 001 May 2018 Figure 4 7 BD71837MWV Reference Board Outline Layer 2 GND Layer 2 is used as power GND It s better to secure the wide plane for large switching currents The parasitic i...

Страница 14: ...HM Co Ltd No 61AN002E Rev 001 May 2018 Figure 4 8 BD71837MWV Reference Board Outline Layer 3 VSYS Layer 3 is used as VSYS power Input for each VR It s better to secure the wide plane for large input c...

Страница 15: ...Design Guide 2018 ROHM Co Ltd No 61AN002E Rev 001 May 2018 Figure 4 9 BD71837MWV Reference Board Outline Layer 4 Layer 4 is used as power traces for each VR It s better to secure the enough width to r...

Страница 16: ...M Co Ltd No 61AN002E Rev 001 May 2018 Figure 4 10 BD71837MWV Reference Board Outline Layer 5 LDO4 LDO1 LDO2 LDO7 LDO3 LDO5 LDO6 Layer 5 is used as the power traces for each LDO It s better to secure t...

Страница 17: ...Platform Design Guide 2018 ROHM Co Ltd No 61AN002E Rev 001 May 2018 Figure 4 11 BD71837MWV Reference Board Outline Layer 6 WDOG_B SD_VSELECT RTC_RESET_B Layer 6 is used for routings of each feedback l...

Страница 18: ...in Table 5 1 Table 5 1 The Maximum Design Powers for BUCK convertors LDOs and the Load Switch Voltage Rail Type Input Voltage Default Output Voltage V Max Current mA Over Current Protection Min mA BU...

Страница 19: ..._OUT BUCK6 3 0A 3 0 to 3 3V 0 1V step BUCK7 1 5A 1 6V to 2 0V 8steps NVCC_DRAM VDD_SOC VDD_ARM VDD_GPU VDD_VPU VDD_DRAM NVCC_SNVS 3P3_PHY GPIO_3V3 VDD_SNVS VDDA_1P8 1P8_PHY GPIO_1V8 VDDA_0P9 0P9_PHY i...

Страница 20: ...ion of the stability for the input level for each buck convertor so the design for each input should be also taken care It is highly recommended to follow the all guidelines in this section 5 2 1 Over...

Страница 21: ...e minimize the impedance of the each loop Figure 5 3 shows the current loops to be designed carefully As Figure 5 4 shows the patterns which handle the heavy currents should be routed as much shortly...

Страница 22: ...t can be referred to for your reference 5 2 5 Other Signal Pattern Precautions Make sure to leave adequate space between noisy lines of voltage rail and serial interface I2C 5 2 6 Feedback Sense Lines...

Страница 23: ...8 5 2 7 AGND layout AGND is recommended not to be connected to PGND for PMIC exposed pad directly to avoid noise effect It s better to short AGND to a GND at inner GND plane stable GND through PTH The...

Страница 24: ...the system As a decoupling capacitor use one 10 F Select the input capacitor with the capacitance 3 5 F including the DC bias effect at VSYS 5 0V The recommended part of capacitor is shown below A LMK...

Страница 25: ...be connected to near output capacitors Figure 5 8 BUCK1 Layout Example Top Layer 5 3 2 BUCK2 VDD_ARM BUCK2 is a high efficiency buck converter which converts VSYS 2 7V to 5 5V voltage to a regulated...

Страница 26: ...d area and cost restrictions The recommended part of inductor is shown below A HMLE32251E R47MSR size 3225 Rated DC Current 7 2A As output capacitors use two 22 F capacitors Select the output capacito...

Страница 27: ...tance 1 88 F including the DC bias effect at VSYS 5 0V The recommended part of capacitor is shown below A LMK107BJ475MA size 1608 capacitance 4 7 F tolerance 10V BUCK3_LX 1 0 O Connect to BUCK3 via th...

Страница 28: ...y 2018 5 3 3 3 Layout Example About the parts placement for each capacitor around BUCK3 the below reference layout can be referred to BUCK3_FB should be connected to near output capacitors Figure 5 12...

Страница 29: ...capacitance 1 88 F including the DC bias effect at VSYS 5 0V The recommended part of capacitor is shown below A LMK107BJ475MA size 1608 capacitance 4 7 F tolerance 10V BUCK4_LX O Connect to BUCK3 via...

Страница 30: ..._FB should be connected to near output capacitors Figure 5 14 BUCK4 Layout Example Top Layer 5 3 5 BUCK5 VDD_DRAM BUCK5 is a high efficiency buck converter which converts VSYS 2 7V to 5 5V voltage to...

Страница 31: ...8 capacitance 10 F tolerance 10V BUCK5_LX 1 0 O Connect to BUCK5 via the inductor Connect one 0 47 H 20 inductors to BUCK5_LX 1 0 Select the inductor to be used according to board area and cost restri...

Страница 32: ...uld be connected to near output capacitors Figure 5 16 BUCK5 Layout Example Top Layer 5 3 6 BUCK6 NVCC_3P3 BUCK6 is a high efficiency buck converter which converts VSYS 2 7V to 5 5V voltage to a regul...

Страница 33: ...via the inductor Connect one 1 0 H 20 inductors to BUCK6_LX 1 0 Select the inductor to be used according to board area and cost restrictions The recommended part of inductor is shown below A MAMK2520H...

Страница 34: ...itor with the capacitance 1 88 F including the DC bias effect at VSYS 5 0V The recommended part of capacitor is shown below A LMK107BJ475MA size 1608 capacitance 4 7 F tolerance 10V BUCK7_LX O Connect...

Страница 35: ...y 2018 5 3 7 3 Layout Example About the parts placement for each capacitor around BUCK7 the below reference layout can be referred to BUCK7_FB should be connected to near output capacitors Figure 5 20...

Страница 36: ...h the capacitance 3 5 F including the DC bias effect at VSYS 5 0V The recommended part of capacitor is shown below A LMK107BBJ106MALT size 1608 capacitance 10 F tolerance 10V BUCK8_LX 1 0 O Connect to...

Страница 37: ...y 2018 5 3 8 3 Layout Example About the parts placement for each capacitor around BUCK8 the below reference layout can be referred to BUCK8_FB should be connected to near output capacitors Figure 5 22...

Страница 38: ...t source will be changed from VSYS to BUCK6 automatically LDO3 output voltage is programmable and its voltage range is from 1 8V to 3 3V by 100mV step 5 4 4 LDO4 VDDA_0P9 VLDO4 converts VSYS 2 7V to 5...

Страница 39: ...part of capacitor is shown below A JMK105BJ105MV F size 1005 capacitance 1 0 F tolerance 6 3V LDO2 VDD_SNVS Vout 0 9V 0 8V Iomax 10mA LDO2 O As the output capacitor use one 1 F capacitor Select the ou...

Страница 40: ...e 6 3V LDO7 3 3V PHY Vout 1 8V 3 3V Iomax 150mA LDO7 O As the output capacitor use one 2 2 F capacitor Select the output capacitors within the capacitance range defined in the datasheet of BD71837MWV...

Страница 41: ...nput for MUXSW and connect to BUCK7 As the input capacitor use one 4 7 F capacitor The recommended part of capacitor is shown below A JMK105BBJ475MV F size 1005 capacitance 4 7 F tolerance 6 3V MUXSW_...

Страница 42: ...aluation 5 6 1 1 Schematic Examples Figure 5 25 Crystal Oscillator Driver Schematic Example 5 6 1 2 Schematic Checklist Table 5 12 Schematic checklist of crystal oscillator driver Pin Names Dir Notes...

Страница 43: ...l oscillator driver circuit is extremely sensitive to external environment like parasitic capacitance due to the long wirings for XIN and XOUT So it is recommended to position the Crystal oscillator p...

Страница 44: ...nd I2C interface Capacitor for decoupling use one 1 0 F 20 size 1005 capacitance 1 0 F tolerance 6 3V SCL I DVDD Pulled up to DVDD with 1kohm Connect to SoC Note If pull up resistor is prepared within...

Страница 45: ...hm NC Connect to SoC Note3 If pull up resistor is prepared within SoC the additional pull up resistor is not needed PMIC_STBY_REQ I DVDD Refer to Notes Connect to SoC Note4 PMIC_ON_REQ I DVDD Refer to...

Страница 46: ...Pin Names Dir Signal Voltage Level Notes Check MISC AGND GND Connect to PGND at inner GND plane EXP PADs PGND0 4 GND Connect to the inner GND plane with lower impedance Note The package has one pad a...

Страница 47: ...hnical information The Products specified in this document are not designed to be radiation tolerant For use of our Products in applications requiring a high degree of reliability as exemplified below...

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