86
Sirius-PJ1Training
Slide 86
Display Port Signal Processing
Display Port IN (M2401)
CLK,DE,H,V,FIELD
RGB 10bit x3
I2S
I2C
I2C
IC2404
VPP1101
Display Port
Receiver
(with HDCP)
IC2403
EEPROM
IC2801
EP3C16F484C8N
SyncDet(FPGA)
The digital signal which is input to the Display Port terminal is transmitted to the
Display Port Receiver IC (IC2404) and converted to RGB 10-bit digital video
signals, clock signal, horizontal/vertical sync signal, DE signal, and FIELD signal,
then input to SyncDet (IC2803).
In addition, the audio signal is converted to Master Clock (MCLK), Bit Clock
(BCLK), Word Clock (WCLK), and Data (DO), then input to SyncDet.
This Receiver IC is equipped with a HDCP function. If the video output device is
also equipped with a HDCP function, the encryption unlock is processed
between the video output device and the Receiver IC, and when encryption is
unlocked, the device can output the video. If not unlocked, the video will not be
output.
In addition, the external EEPROM (IC2403) stores EDID data and firmware for
the Display Port.
