RL78/I1D
Operation state switching IAR
R01AN3597EJ0100 Rev.1.00
Page 24 of 42
Jan. 31, 2017
4.7.7. Clock output initialization
Figure 4.8 shows the flowchart of clock output initialization.
Figure 4.8
clock output initialization
4.7.8. INTP0 initialization
Figure 4.9 shows the flowchart of INTP0 initialization.
R_INTP0_Create
return
INTPn interrupt disabled
Clear INTPn interrupt request flag
PMK6-PMK0 bit
1
PIF6-PIF0 bit
0
INTP0 valid edge setting:
Enable the falling edge
INTP0 interrupt priority:
Set to level 3(lowest)
PPR10 bit
1
PPR00 bit
1
EGN0 bit
1
EGP0 bit
0
Figure 4.9
INTP0 initialization
