RL78/I1D
Operation state switching IAR
R01AN3597EJ0100 Rev.1.00
Page 22 of 42
Jan. 31, 2017
System clock control register (CKC)
f
CLK
initial value: High-speed on-chip oscillator clock (f
IH
)
Setting up the CPU/peripheral hardware clock (f
CLK
)
Symbol: CKC
7
6
5
4
3
2
1
0
CLS
CSS
MCS
MCM0
0
0
MCS1
MCM1
0
0
0
0
0
0
0
0
Bit 6
CSS
Selection of CPU/peripheral hardware clock (f
CLK
)
0
Main system clock (f
MAIN
)
1
Subsystem clock (f
SUB
)
Bit 4
MCM0
Main system clock (f
MAIN
) operation control
0
Selects the high-speed on-chip oscillator clock (f
IH
) as the main system
clock (f
MAIN
)
1
Selects the high-speed system clock (f
MX
) as the main system clock (f
MAIN
).
Bit 0
MCM1
Main system clock (f
MAIN
) operation control
0
High-speed on-chip oscillator clock
1
Middle-speed on-chip oscillator clock
Caution: For details on the register setup procedures, refer to RL78/I1D User's Manual: Hardware.