RL78/I1D
Operation state switching IAR
R01AN3597EJ0100 Rev.1.00
Page 34 of 42
Jan. 31, 2017
4.7.17.
A/D converter initialization
Figure 4.20 shows the flowchart of A/D converter initialization.
R_ADC_Create
ADM0 register
00H
return
INTAD interrupt disable
ADMK bit
1: A/D conversion complete interrupt disable
Clear INTAD interrupt request flag
ADIF bit
0: Interrupt request flag clear
A/D converter interrupt priority level 0 setting
ADM0 register
14H
FR2-FR0 bit=010B
: f
CLK
/8 (f
CLK
=8 MHz)
ADMD bit=0 : Select mode
ADM1 register
00H
ADTMD1-ADTMD0 bits= 00B :Software trigger mode
ADUL register
FFH
Conversion result comparison upper value setting
ADLL register
00H
Conversion result comparison lower value setting
ADS register
81H
ADS4-ADS0 bits = 00001B
ADISS bit = 1
ADM2 register 00H
ADTYP = 0
:
12-bit resolution
ADREFP1-ADREF0 bits = 00B :Provide from AV
DD
ADREFM = 0 :Provide from AV
SS
A/D converter clock provision
PER0 register
ADCEN bit
1: Start input clock provision
A/D converter circuit operation stop
A/D converter initialization
Set conversion time about 76us
Set select mode
Set software trigger mode
Set one shot conversion mode
Reference voltage power supply setting
12-bit resolution
Set + side power supply from AV
DD
Set
–
side power supply from AV
SS
Conversion result comparison upper/Lower limit setting
Set comparison upper limit value to FFH
Set comparison lower limit value to 00H
Analog input channel/ input source definition
Set analog input source to internal reference
voltage (1.45V)
ADPR0 bit
0
ADPR1 bit
0
Reset control of A/D converter
PRR0 register
ADCRES bit
1: A/D converter reset state
ADCRES bit
0: A/D converter reset release
Figure 4.20
A/D converter initialization