Renesas RL78/I1D, Примечание к применению

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RL78/I1D Operation state switching IAR
R01AN3597EJ0100 Rev.1.00 Page 36 of 42
Jan. 31, 2017
4.7.20. Flash operation mode switching (LP) processing
Figure 4.23 shows the flowchart of the flash operation mode switching (LP) processing.
switch_flashmode_to_LP
return
Set the middle-speed on-chip
oscillator clock frequency to 1MHz
MOCODIV register 02H
Middle-speed on-chip oscillator
operating
MIOEN bit 0 : Middle-speed on-chip oscillator operating
MCS1 = 0?
Yes
No
Main on-chip oscillator clock status in the case of
high-speed on-chip oscillator clock, switch to
the middle-speed on-chip oscillator clock.
Set the middle-speed on-chip
oscillator clock to
the main on-chip oscillator clock
MCM1 bit 1 : Select middle-speed on-chip oscillator clock
MCS1 = 1?
Yes
No
Set the high-speed on-chip oscillator
to stop
HIOSTOP bit 1 : High-speed on-chip oscillator stop
Wait until the status of the main on-chip oscillator clock is
switched to the middle-speed on-chip oscillator clock
Set the regulator mode to
the normal setting
PMMC register
MCSEL bit 0
g_flash_mode _08_FLAHMODE_LP
Set flash operation mode to
LP (low-power main) mode
FLMWEN bit 1 :Rewriting the FLMODE register is enabled
FLMODE register 40H : LV (low-power main) mode
FLMWEN bit 0 : Rewriting the FLMODE register is disabled
Updated status flag variable of
flash operation mode
Set the regulator mode to
the low-power consumption setting
PMMC register
MCSEL bit 1
Figure 4.23 Flash operation mode switching (LP normal) processing