Renesas RA Family
RA2 Quick Design Guide
R01AN6060EU0100 Rev.1.00
Page 27 of 44
Sep.14.21
9.2.1 Internal Pull-Ups
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Most pins on ports 0 through 9 can enable a pull-up resistor. The pull-up is controlled by the Pull-Up bit
(PCR) bit in each Port mn Pin Function Select (PmnPFS) Register. The PCR bit in each PmnPFS register
controls the corresponding pin on the port.
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The pin must first be set as an input with the associated bit in the PmnPFS register. Set the PCR bit to “1”
to enable the pull-up and to “0” to disable it.
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Out of reset all PCR registers are cleared to 0, therefore all pull-up resistors are disabled.
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The pull-up is automatically turned off whenever a pin is designated as an external bus pin, a GPIO
output, or a peripheral function output pin.
9.2.2 Open-Drain Output
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Pins configured as outputs normally operate as CMOS outputs.
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Most pins on ports 0 through 9 can be configured as an NMOS open-drain output.
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The N-channel open-drain control (NCODR) bit in each Port mn Pin Function Select (PmnPFS) Register
controls which pins operate in open-drain mode. Setting the applicable bit in each register to a “1” makes
the output open-drain. Setting the applicable bit in each register to a “0” sets the port to CMOS output.
9.2.3 Drive Capacity
The RA2A1 MCU group can enable an output drive capacity. For RA2A1, the drive capacity can be set to
low- or middle-drive capacity. The other RA2 MCU groups don’t have this capability.
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Drive capacity switching is controlled by the Drive Capacity Control Register (DSCR) bits in each Port mn
Pin Function Select (PmnPFS) register.
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Out of reset, all DSCR registers are cleared to 0. Therefore all pins are set to low drive output. Setting a
value other than “00” will change the drive capacity of the output for the selected pin.
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The maximum total output of all pins is dependent on the specific MCU group and device package.
Please see the “Electrical Characteristics” section of the Hardware User’s Manual for details.
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The typical differences the drive levels are shown below. Actual output current levels vary by device and
pin type. See the specific MCU Hardware User’s Manual for details.
Table 10. Differences in Drive Levels
Typical output pins
DSCR[1:0]
Drive Capacity
Max (mA)
Permissible output current per pin
0 0
Low Drive
4.0
Permissible output current per pin
0 1
Middle Drive
8.0
IIC Fast Mode and SPI
1 0
Middle Drive
8.0
Invalid setting; do not use
1 1
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Output drive capacity can have a significant impact on overall performance of a board design. The following
points should be considered when selecting the drive capacity for each output.
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It is recommended to start with all pins set to low-drive capacity (default) and evaluate the performance.
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Depending on the board layout, pins set to middle-drive capacity may result in higher EMI radiation.
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Long traces may require higher drive capacity for signals to propagate correctly to the receiver.
9.3 Setting Up and Using Port Peripheral Functions
The Port mn Pin Function Select Registers (PmnPFS) are used to configure the characteristics of each port.
The PSEL bits select the peripheral function selected for each port.
