Renesas RA Family
RA2 Quick Design Guide
R01AN6060EU0100 Rev.1.00
Page 31 of 44
Sep.14.21
(requires the program to set up the port) but it does limit the effect of accidental pin shorts to ground,
adjacent pins or VCC since the device will not be driving the pin.
9.6 Nonexistent Pins
Each RA2 MCU group is available in multiple package sizes, with different total pin counts. For any package
smaller than the largest package for that MCU group (typically 100 pins, 64 pins, or 24 pins), set the
corresponding bits of nonexistent ports in the PDR register to “1” (output) and in the PODR register to “0”.
The user can see which ports are available on each MCU package by reviewing the “Specifications of I/O
Ports” table in the I/O Ports section of the Hardware User’s Manual. For example, P007 and P008 on port 0
are only available on 100-pin packages. Note that no additional handling of nonexistent pins is required.
9.7 Electrical Characteristics
Normal GPIO ports typically require CM
OS level inputs (High ≥
0.8 * VCC, Low
≤ 0.2
* VCC). Some GPIO
ports have Schmitt Trigger inputs, which have slightly different input requirements. See the Hardware User’s
Manual section “Electrical Characteristics” for more information.
10. Module Stop Function
To maximize power efficiency, the RA2 series of MCUs allow on-chip peripherals to be stopped individually
by writing to the Module Stop Control Registers (MSTPCRi, i=A, B, C, D). Once a module stops, access to
the module registers is not possible.
After a reset, most of the modules are placed in module-stop state, except for DTC. See Hardware User’s
Manual for details.
Before accessing any of the registers for a peripheral, it must be enabled by taking it out of stop mode by
writing a ‘0’ to the corresponding bit in the MSTPCRi register.
Peripherals may be stopped by writing a ‘1’ to the proper bit in the MSTPCRi register.
HAL drivers in Renesas FSP handle module start/stop function automatically.
11. Interrupt Control Unit
The Interrupt Controller Unit (ICU) controls which event signals are linked to the Nested Vector Interrupt
Controller (NVIC) and Data Transfer Control (DTC) modules. The ICU also controls non-maskable interrupts.
Figure 23 shows an example of the ICU specifications, and Figure 24 shows an example of the ability to
raise the IRQi event from the I/O pins. Refer to the Hardware User’s Manual for details for each RA2 MCU
Group.
