Renesas RA Family
RA2 Quick Design Guide
R01AN6060EU0100 Rev.1.00
Page 18 of 44
Sep.14.21
Table 8. RA2 Device Resets
Reset Name
Source
Pin reset
RES# is driven low
Power-on reset
VCC rises (voltage detection: VPOR)
Independent watchdog timer reset The independent watchdog timer underflows, or a refresh occurs
Watchdog timer reset
The watchdog timer underflows, or a refresh occurs
Voltage monitor 0 reset
VCC falls (voltage detection Vdet0)
Voltage monitor 1 reset
VCC falls (voltage detection Vdet1)
Voltage monitor 2 reset
VCC falls (voltage detection Vdet2)
SRAM parity error reset
SRAM parity error detection
SRAM ECC error reset
*1
SRAM ECC error detection
Bus master MPU error reset
Bus master MPU error detection
Bus slave MPU error reset
Bus slave MPU error detection
Stack pointer error reset
Stack pointer error detection
Software reset
Register setting
Note 1: Not present on RA2E1 or RA2E2 devices.
6.1 Pin Reset
When the RES# pin is driven low, all processing is aborted and the MCU enters a reset state. To reset the
MCU while it is running, RES# should be held low for the specified reset pulse width. Refer to the “Reset
Timing” section of the “Electrical Characteristics” chapter of the Hardware User’s Manual for more detailed
timing requirements. Also refer to section 2 of this document, “Emulator Support” for details on reset circuitry
in relation to debug support.
There is no need to use an external capacitor on the RES# line because the POR circuit holds it low
internally for a good reset and a minimum reset pulse is required to initiate this process.
6.2 Power-On Reset
There are two conditions that will generate a power-on reset (POR):
1. If the RES# pin is in a high-level state when power is supplied.
2. If the RES# pin is in a high-level state when VCC is below V
POR.
After VCC has exceeded the power-on reset voltage (V
POR
) and the power-on reset time (t
POR
) has elapsed,
the chip is released from the power-on reset state. The power-on reset time is a period that allows for
stabilization of the external power supply and the MCU. Refer to the “POR and LVD Characteristics” section
of the “Electrical Characteristics” chapter of the Hardware User’s Manual for voltage level and timing details.
Because the POR circuit relies on having RES# high concurrently with VCC, don’t place a capacitor on the
reset pin. This will slow the rise time of RES# in relation to VCC, preventing the POR circuit from properly
recognizing the power-on condition.
If the RES# pin is high when the power supply (VCC) falls to or below V
POR
, a power-on reset is generated.
The chip is released from the power-on state after VCC has risen above V
POR
and the t
POR
has elapsed.
After a power on reset, the PORF bit in RSTSR0 is set to 1. Following a pin reset, PORF is cleared to 0.
6.3 Independent Watchdog Timer Reset
This is an internal reset generated by the Independent Watchdog Timer (IWDT).
When the IWDT underflows, an independent watchdog timer reset is optionally generated (NMI can be
generated instead) and the IWDTRF bit in RSTSR1 is set to a 1. After a short delay the IWDT reset is
canceled. Refer to MCU User’s Manual for the specific timing.
6.4 Watchdog Timer Reset
This is an internal reset generated by the Watchdog Timer (WDT).
When the WDT overflows, a watchdog timer reset is optionally generated (NMI can be generated instead),
and the WDTRF bit in RSTSR1 is set to a 1. After a short delay the WDT reset is canceled. Refer to MCU
User’s Manual for the specific timing.
