User’s Manual U14481EJ3V0UM
33
CHAPTER 4 CAUTIONS
4.1 Cautions on Terminating Pins
The pins that perform special processing in the emulator are explained below.
For detailed circuit configuration, refer to
CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICES AND
TARGET INTERFACE CIRCUITS
.
(1) Pins that cannot be emulated
The following pins cannot be emulated because they are left open inside the emulator or connected to 3.3 V or
GND via resistor. Evaluate these pins by using the target device.
Table 4-1. Pins That Cannot Be Emulated
Pin Name 1
Target Device
Pin No.
V850E/MA1 (144-pin LQFP)
58
V850E/MA1 (161-pin FBGA)
M8
MODE0
V850E/MA2 (100-pin LQFP)
36
V850E/MA1 (144-pin LQFP)
57
V850E/MA1 (161-pin FBGA)
P8
MODE1
V850E/MA2 (100-pin LQFP)
35
V850E/MA1 (144-pin LQFP)
18
V850E/MA1 (161-pin FBGA)
G1
MODE2
V850E/MA2 (100-pin LQFP)
21
V850E/MA1 (144-pin LQFP)
62
V850E/MA1 (161-pin FBGA)
N9
X2
V850E/MA2 (100-pin LQFP)
40
V850E/MA1 (144-pin LQFP)
61
V850E/MA1 (161-pin FBGA)
P9
CV
DD
V850E/MA2 (100-pin LQFP)
39
(2) X1 pin
The X1 pin is pulled down using 33 k
Ω
when an external clock is selected.
Because the external clock is input to the clock generator via 74HC157, a delay time of up to 13.2 ns is
generated.
This pin is pulled down using 33 k
Ω
and is left open when the internal clock is selected.
(3) CKSEL pin
The CKSEL pin can be pulled up or down, depending on the setting of SW1.
It is pulled down using 33 k
Ω
when “PLL” is selected by SW1. This pin is pulled up using 33 k
Ω
when “DIRECT”
is selected.