PPC7A Product Manual
Functional Description
8-37
1
st
Edition
PCI Configuration
The boot process must configure the base address and space type (memory or I/O) of all the PCI attached
peripherals. The memory requirements of each PCI device are given in the appropriate device
descriptions in this chapter.
Each PCI device also has several registers located in PCI configuration space, which is accessed by the
processor through the GT64260 PCI bridge and memory controller using the CONFIG_ADDR and
CONFIG_DATA registers. A full description of PCI configuration can be found in the GT64260
specifications.
The device number mapping for the PCI bus 0 attached to the GT64260 is as follows:
D
EVICE
N
O
.
F
UNCTION
0 to 15
Not implemented
16
53C860 SCSI controller
17
Not implemented
18
South bridge
19
Not implemented
20
Universe II VME controller
21
Graphics
22 to 30
Not implemented
The device number mapping for the PCI bus is as follows:
D
EVICE
N
UMBER
F
UNCTION
0 TO 22
Not implemented
23
PMC2
24
PMC1
25 TO 30
Not implemented
Keylock
The keylock input signal allows the software to interrogate an external keyswitch. For example, the boot
firmware could request a password if the keyswitch is in the locked position and a password is set up in
the NVRAM.
The keylock signal defaults to high if no external connection is made.
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