PPC7A Product Manual
Connectors
5-6
1
st
Edition
VMEbus Signal Descriptions
The VMEbus signals occupy rows a, b and c of the P1 connector and row b of the P2 connector.
M
NEMONIC
S
IGNAL
D
ESCRIPTION
A01 to A15
Address Bus (bits 1 to 15). Address lines that are used to broadcast a short address
A16 to A23
Address Bus (bits 16 to 23). Address lines that are used with A01 to A15 and LWORD~ to broadcast a standard
address
A24 to A31
Address Bus (bits 24 to 31). Address lines that are used with A01 to A23 and LWORD~ to broadcast an extended
or 64-bit address
ACFAIL~
AC Failure. This shows that the AC input to the power supply is no longer being provided or that the required AC
input voltage levels are not being met
AM0 to AM5
Address Modifier (bits 0 to 5). These are used to broadcast information such as the address size, cycle type,
master identification or any combination of these
AS~
Address Strobe. This shows when a valid address has been placed on the address bus
BBSY~
Bus Busy. This is driven low by the requester associated with the current bus master to show that the master is
using the bus
BCLR~
Bus Clear. This is generated by an arbiter to show that there is a higher priority request for the bus than the one
being processed. This requests the current master to release the bus
BERR~
Bus Error. This is generated by a slave or bus timer to tell the master that the data transfer did not complete
BG0IN~ to BG3IN~
Bus Grant (0 to 3) In. These signals are generated by the arbiter to tell the board receiving it that if it is requesting
the bus on that level, then it has been granted use of the bus. Otherwise the board should pass the signal down
the daisy chain. The BGxIN~/BGxOUT~ signals form the bus grant daisy chain, i.e. the BGxOUT~ of one board
forms the BGxIN~ of the next board in the daisy chain
BG0OUT~ to BG3OUT~
Bus Grant (0 to 3) Out. These signals are generated by requesters to tell the next board in the daisy chain that if it
is requesting the bus on that level, then it can use the bus. Otherwise the board should pass the signal down the
daisy chain
BR0~ to BR3~
Bus Request (0 to 3). A low level, generated by a requester, on one of these lines, shows that some master needs
to use the bus.
D00 to D31
Data Bus. These are used to transfer data between masters and slaves, and status/ID information from
interrupters to interrupt handlers
DS0~, DS1~
Data Strobe 0, 1. These are used with LWORD~ and A01 to show how many byte locations are being accessed
(1, 2, 3 or 4). Also, during a write cycle, the falling edge of the first data strobe shows that valid data is available
on the bus. On a read cycle, the rising edge of the first data strobe shows that data has been accepted from the
data bus
DTACK~
Data Transfer Acknowledge. This signal is generated by a slave. The falling edge shows that valid data is
available on the data bus during a read cycle, or that data has been accepted from the data bus during a write
cycle. The rising edge shows that the slave has released the data bus at the end of a read cycle
GND
The DC voltage reference for the system
IACK~
Interrupt Acknowledge. This is used by the interrupt handler to acknowledge an interrupt request. It is routed to
the IACKIN~ pin of slot 1, where it is monitored by the IACK daisy chain driver
IACKIN~
Interrupt Acknowledge In. This tells the board receiving it that that board can respond to the interrupt
acknowledge cycle in process or pass it down the daisy chain. IACKIN~/IACKOUT~ form the interrupt
acknowledge daisy chain
IACKOUT~
Interrupt Acknowledge Out. This is sent by a board to tell the next board in the daisy chain that it can respond to
the interrupt acknowledge cycle in progress
IRQ1~ to IRQ7~
Interrupt Request (1 to 7). These are driven low by interrupters to request an interrupt on the corresponding level
LWORD~
Longword. This is used with DS0~, DS1~ and A01 to select which byte location(s) within the 4-byte group are
accessed during the data transfer
Reserved
This signal is reserved for future enhancements of the VME specification
SERA
The serial clock used to synchronise the data transmission on the serial bus
SERB
This is used for serial data transmission
SYSCLK
System Clock. This provides a constant 16 MHz clock signal that is independent of any other bus timing
SYSFAIL~
System Fail. This shows that a failure has occurred in the system. This signal can be generated by any board in
the system
SYSRESET~
System Reset. When this is low, it causes the system to be reset
Continued over leaf.
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