PPC7A Product Manual
Functional Description
8-10
1
st
Edition
JTAG Clock Frequencies
Different parts in the JTAG chain may have different maximum TCK frequencies. The main chain on the
PPC7A
has the following clock limitations:
Universe II
⇒
20 MHz
GT64260
⇒
3 MHz
L2 or L3 cache
⇒
50 MHz
PowerPC 7410/745x
⇒
33 MHz
The JTAG clock should not exceed the maximum clock frequency of the slowest element in the JTAG
chain. Using the data from the above components, the chain clock frequency should not exceed
10 MHz.
JTAG and PMC
The “MAIN” JTAG chain from J11 & J12 visits the other PMC site. These individually auto-bypass if a
PMC is not fitted at the site. To achieve this, the PPC7A
has BUSMODE2 to BUSMODE4 wired to 1, 0,
0 respectively. This effectively interrogates the PMC site as to whether it has a PCI compliant card fitted.
The response from the PMC is returned on BUSMODE1. If the answer is yes (BUSMODE1 = 0), then
the PMC site is included in the JTAG chain. If there is no PMC fitted, then a pull-up resistor on the
PPC7A
forces BUSMODE1 to 1 and the JTAG is bypassed.
$
Notes:
1.
The PCI specification (section 2.2.10 on the optional JTAG pins) requires that if a PMC cannot support JTAG,
then it must have TDI connected to TDO. This means that the “MAIN” JTAG chain is complete even if there
are PMC cards fitted that do
not
support JTAG.
2.
The PMC sites cannot
source
the JTAG since, being part of a chain, they are expected to
receive
the JTAG
signals.
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