PPC7A Product Manual
Functional Description
8-35
1
st
Edition
Interrupts and Error Reporting
The following table shows the various external interrupt sources to the processor and their relative
priorities. It also shows whether the previous state of the processor is recoverable.
P
RIORITY
I
NTERRUPT
C
AUSE
R
ECOVERABILITY
0
System Reset
Power on,
Hard reset
Non-recoverable
1
Machine Check
Address or Data Parity error,
Machine Check Input (MCP~),
Non-maskable Interrupt (NMI~)
Non-recoverable in most cases
2
System Reset
Soft reset
Recoverable unless Machine Check occurs
3
System
Management
Interrupt
SMI~ input
Recoverable unless Machine Check or
System Reset occurs
4
External Interrupt
INT~ input
Recoverable unless Machine Check or
System Reset occurs
System Resets
See the
Resetting the PPC7A
section at the start of this chapter.
Machine Check Exception
The South Bridge can be configured the signal NMI on certain conditions. The hardware on the PPC7A
routes this signal to the CPU as the MCP~ (Machine Check) interrupt.
The South Bridge can drive this signal due to the following conditions:
•
PCI bus error
•
PCI SERR~ signal driven active
The PCI SERR~ signal can be driven low by other PCI devices to report a error condition.
The processor may be configured to take a machine check exception or enter the checkstop state.
System Management Interrupt (SMI~)
The System Management Interrupt pin of the CPU is connected to the GT64260. This allows the
GT64260 to interrupt the processor for events such as an SDRAM parity error.
To allow the GT64260 to provide a SMI~ interrupt to the CPU the output pin MPP[8] needs to be set to
Int[0]* (see GT64260 register MPP Control1 - offset - 0xF004). The events that can cause this interrupt
to be driven is by register CPU Int[0]* (0xE60).
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