PPC7A Product Manual
Functional Description
8-15
1
st
Edition
VMEbus Slave Access
Four general-purpose, software-programmable VMEbus slave images are available.
•
All of these may be defined in VMEbus A32, A24 or A16 space
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An offset may be applied to translate the VMEbus address to a different address on the local
bus, allowing any VMEbus address to access any on-board address
•
The start and end addresses of the A32, A24 and A16 images may be set on any 64 Kbyte
boundary
One further, special purpose, VMEbus slave image, the Register Access Slave Image, allows a VMEbus
master to access to the Universe II control and staus registers.
VMEbus slave accesses to the PPC7A
may be coupled, write posted or pre-fetched block read.
•
Coupled slave transfers can only proceed once the slave posted write FIFO is empty
•
Slave posted write cycles are queued in a FIFO until the PCI bus is available for the data to be
transferred
Indivisible Cycles on VME
The Universe II chip may be programmed to generate RMW cycles on the VMEbus. Data from the read
portion is compared with a 32-bit compare value, qualified with a 32-bit mask. If the comparison is true,
then those bits enabled by the mask are swapped with a 32-bit swap field.
Alternatively, the Universe chip’s VMEbus ownership-bit may be set to cause it to acquire and hold
ownership of the VMEbus. This method can be used in combination with VMEbus LOCK cycles to
guarantee exclusive access to a VMEbus resource.
The VMEbus slave images may be programmed to generate locked cycles on the PCI bus to handle
RMW cycles. The Universe II chip also supports VMEbus lock commands using ADOH cycles.
VMEbus Arbitration
The Universe II chip’s VMEbus arbiter supports PRI and RRS arbitration with BCLR~ generation in
priority mode. The VMEbus requester may operate in fair or demand mode and may be configured as
RWD or ROR.
VMEbus Master Block Transfers
The Universe II chip’s DMA controller may be used to transfer data between the PCI bus and the
VMEbus. DMA operations on the two buses are decoupled through a bi-directional FIFO. The DMA
controller can:
•
Transfer multiple blocks of data using entries in a linked-list
•
Pack and unpack data to support differing data widths on the PCI bus and the VMEbus
•
Generate an interrupt on completion or on encountering an error condition
VMEbus Slave Block Transfers
The VMEbus slave interface can respond to D32:BLT and D64:MBLT. For VMEbus slave block
transfers, the Universe II chip may be programmed to pre-fetch read data, which is queued in a FIFO.
Mailboxes
The Universe II contains four 32-bit mailboxes that can generate interrupts on the PCI bus or on the
VMEbus when written to. Each mailbox has separate status, enable and interrupt mapping bits.
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