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40
Rabbit
2000
Microprocessor
uppermost
bit must be zero and the write must be to the first 32k of the memory space.
The
user should see the 9 bytes transmitted at 2400 bps or 416 µs per bit. The status bit
will
initially toggle fairly rapidly during the transmission of the first triplet because the
default
setting of the status bit is to go low on the first byte of an opcode fetch. While the
triplets
are being read instructions are being executed from the small cold boot program
within
the microprocessor. The status line will go low after the first triplet has been read. It
will
go high after the second triplet is finished. It will return to low again after the 3rd trip-
let
is transmitted. and stay that way until the sequence starts again.
If
this test fails to function it may be that the programming connector is connected improp-
erly
or the proper pull-up resistors are not installed on the SMODE lines. Other possibili-
ties
are that one of the oscillators is not working or is operating at the wrong frequency.
The
reset could be failing.
11.3
Diagnostic Test #3
This
test checks the functioning of the RAM connected to /CS1. The test applies the reset,
then
sends a series of triplets to set up the necessary control registers. Then it writes sev-
eral
instructions to RAM. Finally it begins executing instructions in RAM. These instruc-
tions
read and write locations in RAM .
80 14 01
//set MB0CR to 1 to select RAM
80 09 51
//ready watchdog for disable
80 09 54
//disable watchdog timer
//sequence of triplets to write program below to memory
// starting at address zero.
00 01 21
00 02 01
00 03 00
00 04 06
00 05 10
00 06 7e
00 07 29
00 08 10
00 09 FC
00 0A C3
00 0B 00
Содержание 2000
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