3.6.1 The System EC RAM with PMU08
Embedded Controller Command Set
The EC I/F command set allows the OS to communicate with the PMU08.
For detail information refer to ACPI 1.0B specification.
EC I/F Command
Com
mand
Byte
Enco
ding
Byte
Register
R/W
Description
Interrupt
#1
EC_SC
W
Command byte
Header
Interrupt on
IBF=0
#2
EC_DATA
W
Address byte to
read
No Interrupt
Read Embedded
Controller
(RD_EC)
0x80
#3
EC_DATA
R
Read data to
host
Interrupt on
OBF=1
#1
EC_SC
W
Command byte
Header
Interrupt on
IBF=0
#2
EC_DATA
W
Address byte to
write
Interrupt on
IBF=0
Write Embedded
Controller
(WR_EC)
0x81
#3
EC_DATA
W
Data to write
Interrupt on
IBF=0
#1
EC_SC
W
Command byte
Header
No Interrupt
Burst Enable
Embedded Controller
(BE_EC)
0x82
#2
EC_DATA
R
Burst
acknowledge
byte
Interrupt on
OBF=1
Burst Disable
Embedded Controller
(BD_EC)
0x83
#1
EC_SC
W
Command byte
Header
Interrupt on
IBF=0
#1
EC_SC
W
Command byte
Header
No Interrupt
Query Embedded
Controller
(QR_EC)
0x84
#2
EC_DATA
R
Query value to
host
Interrupt on
OBF=1
TECHNICAL SERVICE MANUAL
Prestigio Cavaliere 142
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