PLX Technology PEX 8624-AA RDK, Справочник по аппаратуре

Страница: 8 / 46

PEX 8624-AA RDK Hardware Reference Manual – Version 1.1
Copyright © 2010 by PLX Technology, Inc. All rights reserved
2
1.1 PEX 8624 Features

24-lane, 6-port PCI Express Gen 2 switch with integrated on-chip SerDes

240 GT/s aggregate bandwidth (5.0GT/s/Lane x 24 Lanes x 2 (full duplex))

19mm
2
324-ball Flip-Chip Plastic Ball Grid Array (FCBGA) package

Typical Power – 3.01 W

Cut-Thru packet latency of less than 150ns (x8 to x8)

Low power SerDes (under 90mW per lane)

Fully non-blocking switch architecture

Flexible port configuration
o
Ports configurable as x8 or x4, with auto link-width negotiation to x2 and x1

Flexible device configuration
o
Configurable via serial EEPROM, I
2
C, hardware strapping, or by the host

Maximum packet payload size of 2,048 bytes

Designate any Port as the
Upstream Port
(Port 0 is recommended)

Dynamic Buffer Pool Architecture

Read Pacing (allows user to throttle Read requests from Downstream Ports to allow for more efficient
performance)

Dual casting (enhances performance by sending date from one ingress port to two egress ports)

Dynamic speed (2.5 GT/s or 5.0 GT/s) negotiation

Dynamic link-width negotiation (automatically negotiates down to optimal link-width based on traffic
density)

Lane and polarity reversal

Non-Transparent Bridging support
o
Enables Dual-Host, Dual-Fabric, Host-Failover applications

Conventional PCI-compatible Link Power Management states – L0, L0s, L1, L2/L3 Ready, and L3
(
with
Vaux not supported)

Conventional PCI-compatible Device Power Management states – D0 and D3hot

Active State Power Management

Quality of Service (QoS)
o
One Virtual Channels (VC0) and Eight Traffic classes (TC)
o
Round-Robin and Weighted Round-Robin Port arbitration

Reliability, Availability, Serviceability (RAS) features
o
PCI Express Standard Hot-Plug Controller for three Ports, include optional usage models for
Manually operated Retention Latch, by way of MRL Sensor and Attention Button support
o
Electromechanical Interlock supported with Power Enable output
o
Baseline and Advanced Error Reporting capability
o
Performance Monitoring
 Per-Port Payload and Header Counters
 Per-traffic type (write, Read, Completion) Counters
o
JTAG AC/DC boundary scan
o
6-port link status indicators (PEX_PORT_GOOD[9,8,6,5,1,0]#)
o
14 GPIO and/or Serial Hot-Plug PERST# pins

INTA# (PEX_INTA#) and FATAL ERROR (FATAL_ERR#) (Conventional PCI SERR# equivalent) ball
support

Compliant to the following specifications:
o
PCI Local Bus Specification, Revision 3.0 (PCI r3.0)
o
PCI Bus Power Management Interface Specification, Revision 1.2 (PCI Power Mgmt. r1.2)
o
PCI to PCI Bridge Architecture Specification, Revision 1.2 (PCI-to-PCI Bridge r1.2)
o
PCI Express Base Specification, Revision 1.1 (PCI Express Base r1.1)
o
PCI Express Base Specification, Revision 2.0 (PCI Express Base r2.0)
o
PCI Express Card Electromechanical (CEM) Specification, Revision 2.0
o
PCI ExpressCard CEM r2.0)
o
PCI Express Mini Card Electromechanical (CEM) Specification, Revision 1.1
(PCI ExpressCard Mini CEM r1.1)
o
IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture,
1990 (IEEE Standard 1149.1-1990)