PLX Technology PEX 8624-AA RDK, Справочник по аппаратуре

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PEX 8624-AA RDK Hardware Reference Manual – Version 1.1
Copyright © 2010 by PLX Technology, Inc. All rights reserved
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3.6 I
2
C Port (JP5 – JP6) .................................................................................................................... 21
3.7 ATX HD Power Connector (J1) ................................................................................................. 22
3.8 Reference Clock Header (J2) ..................................................................................................... 22
3.9 Probe Mode Input Header (J3) ................................................................................................... 22
3.10 PLX Use Header (J4) .............................................................................................................. 23
4. Bill of Materials/ Schematics .............................................................................................................24
F
IGURES
Figure 1-1. PEX 8624-AA RDK Front View ............................................................................................. 1
Figure 2-1. PEX 8624-AA RDK Hardware Architecture ........................................................................... 4
Figure 2-2. PCI Express up to 5GT/s Gen 2 Connections .......................................................................... 5
Figure 2-3. Use mini-SAS Connector for NT Function Setup.................................................................... 7
Figure 2-4. PEX 8624-AA RDK Reference Clock Circuit ......................................................................... 7
Figure 2-5. PEX 8624-AA RDK Reset Circuit ........................................................................................... 8
Figure 2-6. PEX 8624-AA RDK PHP Circuits ........................................................................................... 9
Figure 2-7. PEX 8624-AA RDK SERIAL HOT-PLUG Circuits ............................................................. 10
Figure 2-8. PEX 8624-AA RDK Power Subsystem ................................................................................. 11
Figure 3-1. Switch SW1 Default Settings ................................................................................................. 14
Figure 3-2. Switch SW2 Default Settings ................................................................................................. 14
Figure 3-3. Switch SW3 Default Settings ................................................................................................. 15
Figure 3-4. Switch SW4 Default Settings ................................................................................................. 15
Figure 3-5. Switch SW5 Default Settings ................................................................................................. 16
Figure 3-6. Switch SW6 Default Settings ................................................................................................. 16
Figure 3-7. Switch SW7 Default Settings ................................................................................................. 17
Figure 3-8. Switch SW8 Default Settings ................................................................................................. 18
Figure 3-9. Midbus 2.0 footprint Dimensions, pin numbering and specification
(Copied from Agilent’s document) .................................................................................................... 20
T
ABLES
Table 2-1. PEX 8624-AA RDK LED Indicator descriptions ................................................................... 11
Table 2-2. Port Link Status LED Functions.............................................................................................. 12
Table 2-3. Voltage Level Monitoring LED Functions .............................................................................. 13
Table 2-4. Strap_Reserved Pin Connections ............................................................................................ 13
Table 3-1. Switch SW2 Description ......................................................................................................... 14
Table 3-2. Switch SW3 Description ......................................................................................................... 15
Table 3-3. Switch SW5 Description ......................................................................................................... 16
Table 3-4. Switch SW6 Description ......................................................................................................... 17
Table 3-5. Switch SW7 Description ......................................................................................................... 18
Table 3-6. Switch SW8 Description ......................................................................................................... 18
Table 3-7. Signal Names of x8 PCI Express Midbus probe footprint ...................................................... 20
Table 3-8. Midbus probe footprints VS. Lanes of PEX 8624 ................................................................... 21
Table 3-9. Pin assignment of JP4 .............................................................................................................. 21
Table 3-10. Pin assignment of JP5 and JP6 .............................................................................................. 21
Table 3-11. Pin assignment of J1 .............................................................................................................. 22
Table 3-12. Pin assignment of J2 .............................................................................................................. 22
Table 3-13. Pin assignment of J3 .............................................................................................................. 22
Table 3-14. Pin assignment of J4 .............................................................................................................. 23