PLX Technology PEX 8624-AA RDK, Справочник по аппаратуре

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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RX5n_P1
RX6p_P1
RX6n_P1
RX7p_P1
REFCLKp
REFCLKn
RX7n_P1
PERST#_P1
RX3p
RX1p
RX3n
RX1n
RX0p
RX2p
RX2n
RX4p_P1
CTX1p
CTX1n
CTX2p
CTX2n
CTX3p
CTX3n
CTX0p
CTX0n
RX0n
RX4n_P1
RX5p_P1
PRSNT#
TX3p
TX5p_P1
TX5n_P1
TX4p_P1
TX4n_P1
TX6p_P1
TX6n_P1
TX7p_P1
TX7n_P1
OEINV_2
CLKEN#_SL2
HBW_2
BP_2
RCLKP1
CLKEN#_SL1
RCLKN1
CLKEN#_SL2
HBW_2
RCLKP2
RCLKN2
BP_2
SL1_RCKp
SL1_RCKn
SL3_RCKn
SL3_RCKp
RCLKP5
RCLKN5
RCLKP6
RCLKN6
IREF_2
VDDA_2
SS_2
PWD_2
CLKEN#_SL1
REFCLKp_U1
REFCLKn_U1
SL2_RCKp
SL2_RCKn
TX3n
TX2n
TX2p
TX1n
TX1p
TX0n
TX0p
12VCC
3.3VCC 3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
PERST#_P1 {6}
RX0p {2,8}
RX0n {2,8}
RX1p {2,8}
RX1n {2,8}
RX2p {2,8}
RX2n {2,8}
RX3p {2,8}
RX3n {2,8}
RX4p_P1 {2}
RX4n_P1 {2}
RX5p_P1 {2}
RX5n_P1 {2}
RX6p_P1 {2}
RX6n_P1 {2}
RX7p_P1 {2}
RX7n_P1 {2}
TX3p {2,8}
TX4p_P1 {2}
TX4n_P1 {2}
TX5p_P1 {2}
TX5n_P1 {2}
TX6p_P1 {2}
TX6n_P1 {2}
TX7p_P1 {2}
TX7n_P1 {2}
SL1_RCKp {3}
SL1_RCKn {3}
SL3_RCKp {3}
SL3_RCKn {3}
REFCLKp_U1 {9}
REFCLKn_U1 {9}
SL2_RCKp {3}
SL2_RCKn {3}
CLKEN#_SL1 {6}
CLKEN#_SL2 {5}
TX3n {2,8}
TX2n {2,8}
TX2p {2,8}
TX1n {2,8}
TX1p {2,8}
TX0n {2,8}
TX0p {2,8}
Title
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.
870 W Maude Ave, Sunnyvale, CA 94085
B
4 9 Friday, March 26, 2010
www.plxtech.com
Title
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.
870 W Maude Ave, Sunnyvale, CA 94085
B
4 9 Friday, March 26, 2010
www.plxtech.com
Title
Size Document Number Rev
Date: Sheet of
91-0080-000-A 4
PLX TECHNOLOGY, INC.
870 W Maude Ave, Sunnyvale, CA 94085
B
4 9 Friday, March 26, 2010
www.plxtech.com
REFERENCE CLOCK CIRCUITS
PEX8624RDK
PCIE MALE CONNECTOR
R7-R10 SHOUD BE CLOSE TO PIN 6& 7 OF U2
REFCLK CIRCUITS
R11-R14 SHOUD BE CLOSE TO PIN9 & 10 OF U2
R15-R18 SHOUD BE CLOSE TO PIN19 & 20 OF U2
R19-R22 SHOUD BE CLOSE TO PIN22 & 23 OF U2
P5_1/P5_2 to P6_1/P6_2 are probing holes for refclk
signals at P1. They should be placed close to the
connector. See layout requirement on page 3 for details.
R14 49.9, 1% R14 49.9, 1%
C58
0.01uF
C58
0.01uF
P6_1 P6_1
+
C47
22uF
+
C47
22uF
R15 33 R15 33
P1
x8 PCI Express Contr
P1
x8 PCI Express Contr
PRSNT1#
A1
+12V
A2
+12V
A3
GND
A4
TCLK
A5
TDI
A6
TDO
A7
TMS
A8
+3.3V
A9
+3.3V
A10
PERST#
A11
+12V
B1
+12V
B2
+12V
B3
GND
B4
SMCLK
B5
SMDAT
B6
GND
B7
+3.3V
B8
TRST#
B9
3.3VAUX
B10
WAKE#
B11
RSVD
B12
PETp0
B14
PETn0
B15
GND
B16
PRSNT2#
B17
GND
B18
PETp1
B19
PETn1
B20
GND
B21
GND
B22
PETp2
B23
PETn2
B24
GND
B25
GND
B26
PETp3
B27
PETn3
B28
GND
B29
RSVD
B30
GND
A12
A13
REFCLK-
A14
GND
A15
PERp0
A16
PERn0
A17
GND
A18
RSVD
A19
GND
A20
PERp1
A21
PERn1
A22
GND
A23
GND
A24
PERp2
A25
PERn2
A26
GND
A27
GND
A28
PERp3
A29
PERn3
A30
GND
B13
GND
A31
RSVD
A32
RSVD
A33
GND
A34
PERp4
A35
PERn4
A36
GND
A37
GND
A38
PERp5
A39
PERn5
A40
GND
A41
GND
A42
PERp6
A43
PERn6
A44
GND
A45
GND
A46
PERp7
A47
PERn7
A48
GND
A49
PRSNT2#
B31
GND
B32
PETp4
B33
PETn4
B34
GND
B35
GND
B36
PETp5
B37
PETn5
B38
GND
B39
GND
B40
PETp6
B41
PETn6
B42
GND
B43
GND
B44
PETp7
B45
PETn7
B46
GND
B47
PRSNT2#
B48
GND
B49
C55 0.1uF C55 0.1uF
R22 49.9, 1% R22 49.9, 1%
C51 0.1uF C51 0.1uF
U2
CY28400-2
U2
CY28400-2
VDD
1
VDD
5
VDD
11
VDD
18
VDD
24
VSS
4
OE_INV
25
VDD_A
28
VSS_A
27
SRC_IN
2
SRC_IN#
3
OE_1
8
OE_6
21
HIGH_BW#
17
SRC_STP
16
PWRDWN
15
SCLK
13
SDATA
14
IREF
26
PLL/BYPASS#
12
DIFT1
6
DIFC1
7
DIFT2
9
DIFC2
10
DIFT5
20
DIFC5
19
DIFT6
23
DIFC6
22
C50 0.1uF C50 0.1uF
C54 0.1uF C54 0.1uF
R5 4.7K R5 4.7K
P6_2 P6_2
P5_1 P5_1
R19 33 R19 33
R9 49.9, 1% R9 49.9, 1%
R11 33 R11 33
R6
475 1%
R6
475 1%
R7 33 R7 33
C49 0.1uF C49 0.1uF
R4 4.7 R4 4.7
R16 33 R16 33
C60
0.01uF
C60
0.01uF
R13 49.9, 1% R13 49.9, 1%
R17 49.9, 1% R17 49.9, 1%
R8 33 R8 33
C56 0.1uF C56 0.1uF
RN1
4.7K
RN1
4.7K
1
2
3
4 5
6
7
8
C52 0.1uF C52 0.1uF
P5_2 P5_2
C53 0.1uF C53 0.1uF
R21 49.9, 1% R21 49.9, 1%
+ C48
22uF
+ C48
22uF
C57
10uF
C57
10uF
C61
10uF
C61
10uF
R10 49.9, 1% R10 49.9, 1%
C59
0.01uF
C59
0.01uF
R20 33 R20 33
R12 33 R12 33
R18 49.9, 1% R18 49.9, 1%