PEX 8624-AA RDK Hardware Reference Manual – Version 1.1
Copyright © 2010 by PLX Technology, Inc. All rights reserved
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Pin #
Signal Name
Pin #
Signal Name
44 GND 43
C7p-Upstream
46 C7p-Downstream 45 C7n-Upstream
48 C7n-Downstream 47
G2 GND
Table 3-8. Midbus probe footprints VS. Lanes of PEX 8624
Midbus Probe Footprint
Lanes of PEX 8624
JP1
Lane 0 – Lane 7
JP2
Lane 24 – Lane 31
3.4
2.5V Header (JP3)
This 2-pin header provides the mechanism for 2.5 volt measurement, which is for PLX use only. For regular RDKs,
no header will be assembled and instead a wire will be used to connect pin 1-2 of JP7.
3.5
JTAG Header (JP4)
The 2x5 header JP4 provides a direct connection to the PEX 8624 JTAG interface. The 10-pin connector is
designed to allow a direct interface to 3rd party JTAG controllers, such as the Corelis USB-1149.1/E controller.
The pin assignment for the JTAG header (JP4) is listed at
Table 3-9
.
Table 3-9. Pin assignment of JP4
Pin Number
Signal Name
1 JTAG_TRST
3 JTAG_TDI
5 JTAG_TDO
7 JTAG_TMS
9 JTAG_TCK
2,4,6,8,10 GND
3.6
I
2
C
Port (JP5 – JP6)
(See Section
2.7
for details)
Table 3-10. Pin assignment of JP5 and JP6
Pin Number
Signal Name
1 I2C_SCL
2 GND
3 I2C_SDA
4 NC
Содержание PEX 8624-AA RDK
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