PEX 8624-AA RDK Hardware Reference Manual – Version 1.1
Copyright © 2010 by PLX Technology, Inc. All rights reserved
8
2.4 Reset
Circuitry
The PEX 8624-AA RDK reset circuitry includes a MAX6420 adjustable reset timer (U9), a Fairchild 2-input AND
gate NC7S08 (U8) and manual reset push-button switch (S1). The reset timer accepts PERST# from the card
edge (P1) and from S1 (logical-OR via U8). The MAX6420 has the capability of adjusting the reset timeout period
by changing the value of C70 (0.001
F
≈
3ms). (See
Figure 2-5
for details)
Figure 2-5. PEX 8624-AA RDK Reset Circuit
2.5 Hot-Plug
Circuits
PEX 8624 provides on-chip Parallel Hot-Plug controllers to downstream ports 1, 5 and 9. The remaining
downstream ports are also Hot-Plug capable through the use of the I2C bus and external I/O expander devices.
The PEX 8624-AA RDK implements Hot-Plug control circuitry for SLOT 1 and SLOT 2. SLOT 1 uses the on-chip
parallel Hot-Plug controller while SLOT 2 uses the Serial Hot-Plug control capability through the I2C and I/O
expander. Note that additional device configuration should be required when using the Serial Hot-Plug capability.
(See Section
2.5.2
and
PEX 8624-AA Data Book
for details)
2.5.1
Parallel Hot-Plug Controller Circuit
PEX 8624-AA RDK uses the Parallel Hot-Plug controller on Port 5 for PCI Express connector SLOT 1. The
parallel hot-plug controller consists of five input elements (HP_BUTTON_B#, HP_MRL_B#, HP_PRSNT_B#,
HP_PWR_GOOD_B, HP_PWRFLT_B#) and five output elements (HP_ATNLED_B#, HP_CLKEN_B#,
HP_PERST_B#, HP_PWREN_B, HP_PWRLED_B#).
Содержание PEX 8624-AA RDK
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