27
XpressGX5LP-SE Reference Manual
Ch.3 XpressGX5LP-SE Features
ddr3_Bank0_d24
AU9
ddr3_Bank1_d24
K27
ddr3_Bank0_d25
AM10
ddr3_Bank1_d25
R27
ddr3_Bank0_d26
AT9
ddr3_Bank1_d26
M27
ddr3_Bank0_d27
AL10
ddr3_Bank1_d27
T27
ddr3_Bank0_d28
AP9
ddr3_Bank1_d28
P28
ddr3_Bank0_d29
AR9
ddr3_Bank1_d29
J27
ddr3_Bank0_d30
AU10
ddr3_Bank1_d30
N27
ddr3_Bank0_d31
AN9
ddr3_Bank1_d31
L27
ddr3_Bank0_d32
AA12
ddr3_Bank1_d32
D30
ddr3_Bank0_d33
AD14
ddr3_Bank1_d33
H31
ddr3_Bank0_d34
AA13
ddr3_Bank1_d34
F30
ddr3_Bank0_d35
AH13
ddr3_Bank1_d35
E31
ddr3_Bank0_d36
AC13
ddr3_Bank1_d36
E30
ddr3_Bank0_d37
AJ13
ddr3_Bank1_d37
G31
ddr3_Bank0_d38
AB13
ddr3_Bank1_d38
G30
ddr3_Bank0_d39
AC14
ddr3_Bank1_d39
C30
ddr3_Bank0_d40
AV14
ddr3_Bank1_d40
N30
ddr3_Bank0_d41
AP13
ddr3_Bank1_d41
L30
ddr3_Bank0_d42
AV13
ddr3_Bank1_d42
R31
ddr3_Bank0_d43
AN13
ddr3_Bank1_d43
K30
ddr3_Bank0_d44
AW14
ddr3_Bank1_d44
M30
ddr3_Bank0_d45
AL13
ddr3_Bank1_d45
J30
ddr3_Bank0_d46
AW13
ddr3_Bank1_d46
R30
ddr3_Bank0_d47
AM13
ddr3_Bank1_d47
L31
ddr3_Bank0_d48
AR14
ddr3_Bank1_d48
J28
ddr3_Bank0_d49
AR15
ddr3_Bank1_d49
P29
ddr3_Bank0_d50
AM14
ddr3_Bank1_d50
J29
ddr3_Bank0_d51
AK14
ddr3_Bank1_d51
R29
ddr3_Bank0_d52
AN14
ddr3_Bank1_d52
L28
ddr3_Bank0_d53
AT15
ddr3_Bank1_d53
V29
ddr3_Bank0_d54
AL14
ddr3_Bank1_d54
K28
ddr3_Bank0_d55
AU15
ddr3_Bank1_d55
U29
ddr3_Bank0_d56
AK12
ddr3_Bank1_d56
E28
ddr3_Bank0_d57
AE11
ddr3_Bank1_d57
C28
Bank 0
Bank 1
FPGA Pin
Signal
FPGA Pin
Signal
Table 9: DDR3L SDRAM pin assignments