PLDA XpressGX5LP-SE, Справочное руководство

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Ch.3 XpressGX5LP-SE Features XpressGX5LP-SE Reference Manual
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3.5 QDR2+ SRAM
The XpressGX5LP-SE features two independent banks of QDR2+ SRAM, each capable of addressing up to
144Mbit in an 18-bit wide datapath. The two mounted devices are GSI G581302DT20GE-450..
Figure 8: QDR2+ SRAM
The following table shows pin assignments for the QDR2+ SRAM:
48 connected to
mPRSNT#1 mPRSNT#2 48 AA37 mPETn7
49 -- GND 49 -- GND
Bank 0 Bank 1
FPGA Pin Signal FPGA Pin Signal
QDR2a_a00 U14 QDR2b_a00 T12
QDR2a_a01 P14 QDR2b_a01 K12
QDR2a_a02 J15 QDR2b_a02 K13
QDR2a_a03 T13 QDR2b_a03 N13
QDR2a_a04 R14 QDR2b_a04 M12
QDR2a_a05 R12 QDR2b_a05 L12
QDR2a_a06 P13 QDR2b_a06 L13
QDR2a_a07 J14 QDR2b_a07 J12
QDR2a_a08 H14 QDR2b_a08 J13
QDR2a_a09 A14 QDR2b_a09 D12
Table 8: QDR2+ SRAM pin assignments
Side B Side A
PCI Express
Pin
FPGA Pin Signal
PCI Express
Pin
FPGA Pin Signal
Table 7: Pin assignments for the PCI Express endpoint connector