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XpressGX5LP-SE Reference Manual
Ch.3 XpressGX5LP-SE Features
3.3 Dedicated
Clocks
The following table describes clock assignments for the board:
Table 6: XpressGX5LP-SE clock assignments
Global Clock inputs
osc_config_FPGA
AV29
LVCMOS25
Single-ended 40MHz clock used for the Max V CPLDs.
Osc3 p/n
AK23/AL23
LVDS
125 MHz CLK used for PCIe Hard IP
Osc4p/n
AE17/AE16
LVDS
100MHz CLK for global CLK network
Osc5 p/n
E34/D34
LVDS
200 MHz CLK dedicated to DDR3L Bank1
Osc7 p/n
AV7/AW7
LVDS
200 MHz CLK dedicated to DDR3L Bank0
Osc8 p/n
J23/J24
LVDS
200 MHz CLK dedicated to QDR2 banks
Gxb Transceiver Clock inputs
Pcie_clk_100MHz p/n
AF34/AF35
HCSL
100 MHz Transceiver RefCLK for PCIe Gen2
Signal
FPGA Pin
Type
Comment
