Ch.3 XpressGX5LP-SE Features
XpressGX5LP-SE Reference Manual
18
The following table shows the memory mapping for the Flash Access Module:
Table 5: Flash Memory Mapping
Name
Size
Address
FPGA Sector 1 or User Sector
(SW1-4 = 1)
64MB
7FF FFFF
400 0000
Sector 0
(SW1-4 = 0)
64MB
3FF FFFF
000 0000
CvP / PR signals (Configuration via protocol / Partial reconfiguration
Cvp_confdone
M13
Cvp_confdone
AT29
pr_done
L12
pr_done
AT30
pr_error
N13
pr_error
AU29
pr_ready
L11
pr_ready
AN29
pr_request
L13
pr_request
AN30
FPGA Configuration Signals
Signal
CPLD
Signal Name/Function
FPGA
Table 4: FPGA and CPLD pin assignments
