Pioneer VSX-AX5Ai-S, Руководство по обслуживанию

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VSX-AX5Ai-S
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5 6 7 8
5 6
7
8
C
D
F
A
B
E
7.2 PARTS
7.2.1 IC
Pin Function
No. Pin Name I/O Pin Function
1 VDDOUT
−
Digital VDD (3.3V)
2 SPDIFOUT IEC60958 output O
3 SDATA3O O MBLA data output (5 ch, 6 ch) (at flow: I2S)
4 SDATA2O O MBLA data output (3 ch, 4 ch) (at flow: I2S)
5 SDATA1O O MBLA data output (1 ch, 2 ch) (at flow: I2S)
6 SDATA0O O MBLA ancillary data output (at flow: I2S)
7 LRCKOUT O MBLA LRCK output
8 BCKOUT O MBLA BCK output (64fs)
9 AMCLKOUT O Master clock output (When AMCLKEN output is LOW, active Hi-Z.)
10 AMCLKEN O When 60958 is selected or OUTPUTEN=L output, active LOW. For external clock control
11 SDERRO O Data error flag output
12 VSSOUT
−
Digital GND
13 VDDOUT
−
Digital VDD (3.3V)
14 SDMUTEO O Data mute flag output MUTE: H
15 SAPCMBCKIN I BCK input when converting SACD to MLPCM
16 SAPCMLRCKIN I LRCK input when converting SACD to MLPCM
17 SAPCMD3IN I DATA3 input when converting SACD to MLPCM
18 SAPCMD2IN I DATA2 input when converting SACD to MLPCM
19 SAPCMD1IN I DATA1 input when converting SACD to MLPCM
20 SACDMKO O SACD master clock output (2.8224MHz)
21 SACDDAO O SACD ancillary data output
22 SACDD0O O SACD data output (L)
23 SACDD1O O SACD data output (R)
24 SACDD2O O SACD data output (C)
25 SACDD3O O SACD data output (Lfe)
26 VSSCORE
−
Digital GND (for inside)
27 VDDCORE
−
Digital VDD (3.3V, for inside)
28 SACDD4O O SACD data output (Ls)
29 SACDD5O O SACD data output (Rs)
30 SACDFRO O SACD frame data output (75Hz)
31 TESTMODE0 I LSI test mode input Normally, "L" fixed
32 TESTMODE1 I LSI test mode input Normally, "L" fixed
33 PLLMODE I VCOCLK division ratio selection Normally, "L"
34 SAPCMMODE I 0: normal, 1: When the data type is SACD, output SAPCM*** input to MLPCM.
35 XVALMODE I 0: 64M•128M bit SDRAM, 1: 256M bit SDRAM
36 RJMSBF I MLPCM output format setting at flow 0: I2S, 1: Right aligned MSB first
37 SEL512 I Master clock selection at flow 0: 768fs, 1: 512fs
38 CONT48 O Output for controlling the oscillator (When FMODE="1" and SEL44K="1", active High)
39 CLK48K I Master clock input of fs48kHz (36.864MHz or 24.576MHz)
40 CLK48KI I Crystal resonator input of fs48kHz (24.576MHz)
41 CLK48KO O Crystal resonator output of fs48kHz (24.576MHz)
42 VSSOUT
−
Digital GND
43 VDDOUT
−
Digital VDD (3.3V)
44 CONT44 O Output for controlling the oscillator (When FMODE="1" and SEL44K="0", active High)
45 CLK44K I Master clock input of fs44.1kHz (33.8688MHz or 22.5792MHz)
46 CLK44KI I Crystal resonator input of fs44.1kHz (22.5792MHz)
47 CLK44KO O Crystal resonator output of fs44.1kHz (22.5792MHz)
48 SELOSC I
L: CLK4XK input selection, H: crystal resonator I/O selection As for the crystal resonator, less than
30MHz are insured.
PD8112A (1394 ASSY: IC301)
• Flow Control IC
• The information shown in the list is basic information and may not correspond exactly to that shown in the schematic diagrams.
PD8112A, PEG040B8, PEG041B, BU4094BCF, PCM2902EG, TSB43CA42, SM5819AF, TA1270BF, TC90A49F
List of IC