VSX-AX5Ai-S
164
1
2
3
4
1
2
3
4
C
D
F
A
B
E
Audio Phase Lock Loops Pins
Test Mode Pins
No.
Pin Name
I/O
Pin Function
7
DIV_VCO
O
Output for external phase detector.
This signal is the divided VCO_CLK. It used by the external phase detector to compare with the REF_SYT
signal. The divide ratios are setup in CFR.
8
PLL_TEST
O
PLL test.
This signal is used for internal TI testing and must be unconnected for normal operation.
6
REF_SYT
O
Output for external phase detector.
This signal represents the SYT match for received audio or DV packets. The phase detector uses it as
input to detect differences between the SYT match and the VCO clock.
5
VCO_CLK
I
Input from VCO.
This signal generates internal audio and DV clocks for receive clock recovery.
Audio frequency: 33.868 MHz or 36.864 MHz.
DV frequency: 30.72 MHz, 27 MHz
No.
Pin Name
I/O
Pin Function
2
TEST_MODE0
I/O
Test mode.
Used for internal TI testing. Must be pulled low for normal operation.
3
TEST_MODE1
I/O
57
TEST_MODE2
I/O
58
TEST_MODE3
I/O
67
TEST4
I/O
Factory test pin.
Must tie to low for normal operation. Recommend connection to ground through a 1 k
Ω
resistor.
68
TEST5
I/O
